0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
0004 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
0005 *
0006 * XPedite5330 3U CompactPCI module based on MPC8572E
0007 */
0008
0009 /dts-v1/;
0010 / {
0011 model = "xes,xpedite5330";
0012 compatible = "xes,xpedite5330", "xes,MPC8572";
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015 form-factor = "3U CompactPCI";
0016 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
0017
0018 aliases {
0019 ethernet0 = &enet0;
0020 ethernet1 = &enet1;
0021 serial0 = &serial0;
0022 serial1 = &serial1;
0023 pci0 = &pci0;
0024 pci1 = &pci1;
0025 pci2 = &pci2;
0026 };
0027
0028 pmcslots {
0029 #address-cells = <1>;
0030 #size-cells = <0>;
0031
0032 pmcslot@0 {
0033 cell-index = <0>;
0034 /*
0035 * boolean properties (true if defined):
0036 * monarch;
0037 * module-present;
0038 */
0039 };
0040 };
0041
0042 xmcslots {
0043 #address-cells = <1>;
0044 #size-cells = <0>;
0045
0046 xmcslot@0 {
0047 cell-index = <0>;
0048 /*
0049 * boolean properties (true if defined):
0050 * module-present;
0051 */
0052 };
0053 };
0054
0055 cpci {
0056 /*
0057 * boolean properties (true if defined):
0058 * system-controller;
0059 */
0060 system-controller;
0061 };
0062
0063 cpus {
0064 #address-cells = <1>;
0065 #size-cells = <0>;
0066
0067 PowerPC,8572@0 {
0068 device_type = "cpu";
0069 reg = <0x0>;
0070 d-cache-line-size = <32>; // 32 bytes
0071 i-cache-line-size = <32>; // 32 bytes
0072 d-cache-size = <0x8000>; // L1, 32K
0073 i-cache-size = <0x8000>; // L1, 32K
0074 timebase-frequency = <0>;
0075 bus-frequency = <0>;
0076 clock-frequency = <0>;
0077 next-level-cache = <&L2>;
0078 };
0079
0080 PowerPC,8572@1 {
0081 device_type = "cpu";
0082 reg = <0x1>;
0083 d-cache-line-size = <32>; // 32 bytes
0084 i-cache-line-size = <32>; // 32 bytes
0085 d-cache-size = <0x8000>; // L1, 32K
0086 i-cache-size = <0x8000>; // L1, 32K
0087 timebase-frequency = <0>;
0088 bus-frequency = <0>;
0089 clock-frequency = <0>;
0090 next-level-cache = <&L2>;
0091 };
0092 };
0093
0094 memory {
0095 device_type = "memory";
0096 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
0097 };
0098
0099 localbus@ef005000 {
0100 #address-cells = <2>;
0101 #size-cells = <1>;
0102 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
0103 reg = <0 0xef005000 0 0x1000>;
0104 interrupts = <19 2>;
0105 interrupt-parent = <&mpic>;
0106 /* Local bus region mappings */
0107 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
0108 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
0109 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
0110 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
0111
0112 nor-boot@0,0 {
0113 compatible = "amd,s29gl01gp", "cfi-flash";
0114 bank-width = <2>;
0115 reg = <0 0 0x8000000>; /* 128MB */
0116 #address-cells = <1>;
0117 #size-cells = <1>;
0118 partition@0 {
0119 label = "Primary user space";
0120 reg = <0x00000000 0x6f00000>; /* 111 MB */
0121 };
0122 partition@6f00000 {
0123 label = "Primary kernel";
0124 reg = <0x6f00000 0x1000000>; /* 16 MB */
0125 };
0126 partition@7f00000 {
0127 label = "Primary DTB";
0128 reg = <0x7f00000 0x40000>; /* 256 KB */
0129 };
0130 partition@7f40000 {
0131 label = "Primary U-Boot environment";
0132 reg = <0x7f40000 0x40000>; /* 256 KB */
0133 };
0134 partition@7f80000 {
0135 label = "Primary U-Boot";
0136 reg = <0x7f80000 0x80000>; /* 512 KB */
0137 read-only;
0138 };
0139 };
0140
0141 nor-alternate@1,0 {
0142 compatible = "amd,s29gl01gp", "cfi-flash";
0143 bank-width = <2>;
0144 //reg = <0xf0000000 0x08000000>; /* 128MB */
0145 reg = <1 0 0x8000000>; /* 128MB */
0146 #address-cells = <1>;
0147 #size-cells = <1>;
0148 partition@0 {
0149 label = "Secondary user space";
0150 reg = <0x00000000 0x6f00000>; /* 111 MB */
0151 };
0152 partition@6f00000 {
0153 label = "Secondary kernel";
0154 reg = <0x6f00000 0x1000000>; /* 16 MB */
0155 };
0156 partition@7f00000 {
0157 label = "Secondary DTB";
0158 reg = <0x7f00000 0x40000>; /* 256 KB */
0159 };
0160 partition@7f40000 {
0161 label = "Secondary U-Boot environment";
0162 reg = <0x7f40000 0x40000>; /* 256 KB */
0163 };
0164 partition@7f80000 {
0165 label = "Secondary U-Boot";
0166 reg = <0x7f80000 0x80000>; /* 512 KB */
0167 read-only;
0168 };
0169 };
0170
0171 nand@2,0 {
0172 #address-cells = <1>;
0173 #size-cells = <1>;
0174 /*
0175 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
0176 * Micron MT29F8G08DAA (2x 512 MB), or Micron
0177 * MT29F16G08FAA (2x 1 GB), depending on the build
0178 * configuration
0179 */
0180 compatible = "fsl,mpc8572-fcm-nand",
0181 "fsl,elbc-fcm-nand";
0182 reg = <2 0 0x40000>;
0183 /* U-Boot should fix this up if chip size > 1 GB */
0184 partition@0 {
0185 label = "NAND Filesystem";
0186 reg = <0 0x40000000>;
0187 };
0188 };
0189
0190 };
0191
0192 soc8572@ef000000 {
0193 #address-cells = <1>;
0194 #size-cells = <1>;
0195 device_type = "soc";
0196 compatible = "fsl,mpc8572-immr", "simple-bus";
0197 ranges = <0x0 0 0xef000000 0x100000>;
0198 bus-frequency = <0>; // Filled out by uboot.
0199
0200 ecm-law@0 {
0201 compatible = "fsl,ecm-law";
0202 reg = <0x0 0x1000>;
0203 fsl,num-laws = <12>;
0204 };
0205
0206 ecm@1000 {
0207 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
0208 reg = <0x1000 0x1000>;
0209 interrupts = <17 2>;
0210 interrupt-parent = <&mpic>;
0211 };
0212
0213 memory-controller@2000 {
0214 compatible = "fsl,mpc8572-memory-controller";
0215 reg = <0x2000 0x1000>;
0216 interrupt-parent = <&mpic>;
0217 interrupts = <18 2>;
0218 };
0219
0220 memory-controller@6000 {
0221 compatible = "fsl,mpc8572-memory-controller";
0222 reg = <0x6000 0x1000>;
0223 interrupt-parent = <&mpic>;
0224 interrupts = <18 2>;
0225 };
0226
0227 L2: l2-cache-controller@20000 {
0228 compatible = "fsl,mpc8572-l2-cache-controller";
0229 reg = <0x20000 0x1000>;
0230 cache-line-size = <32>; // 32 bytes
0231 cache-size = <0x100000>; // L2, 1M
0232 interrupt-parent = <&mpic>;
0233 interrupts = <16 2>;
0234 };
0235
0236 i2c@3000 {
0237 #address-cells = <1>;
0238 #size-cells = <0>;
0239 cell-index = <0>;
0240 compatible = "fsl-i2c";
0241 reg = <0x3000 0x100>;
0242 interrupts = <43 2>;
0243 interrupt-parent = <&mpic>;
0244 dfsrr;
0245
0246 temp-sensor@48 {
0247 compatible = "dallas,ds1631", "dallas,ds1621";
0248 reg = <0x48>;
0249 };
0250
0251 temp-sensor@4c {
0252 compatible = "adi,adt7461";
0253 reg = <0x4c>;
0254 };
0255
0256 cpu-supervisor@51 {
0257 compatible = "dallas,ds4510";
0258 reg = <0x51>;
0259 };
0260
0261 eeprom@54 {
0262 compatible = "atmel,at24c128b";
0263 reg = <0x54>;
0264 };
0265
0266 rtc@68 {
0267 compatible = "st,m41t00",
0268 "dallas,ds1338";
0269 reg = <0x68>;
0270 };
0271
0272 pcie-switch@70 {
0273 compatible = "plx,pex8518";
0274 reg = <0x70>;
0275 };
0276
0277 gpio1: gpio@18 {
0278 compatible = "nxp,pca9557";
0279 reg = <0x18>;
0280 #gpio-cells = <2>;
0281 gpio-controller;
0282 polarity = <0x00>;
0283 };
0284
0285 gpio2: gpio@1c {
0286 compatible = "nxp,pca9557";
0287 reg = <0x1c>;
0288 #gpio-cells = <2>;
0289 gpio-controller;
0290 polarity = <0x00>;
0291 };
0292
0293 gpio3: gpio@1e {
0294 compatible = "nxp,pca9557";
0295 reg = <0x1e>;
0296 #gpio-cells = <2>;
0297 gpio-controller;
0298 polarity = <0x00>;
0299 };
0300
0301 gpio4: gpio@1f {
0302 compatible = "nxp,pca9557";
0303 reg = <0x1f>;
0304 #gpio-cells = <2>;
0305 gpio-controller;
0306 polarity = <0x00>;
0307 };
0308 };
0309
0310 i2c@3100 {
0311 #address-cells = <1>;
0312 #size-cells = <0>;
0313 cell-index = <1>;
0314 compatible = "fsl-i2c";
0315 reg = <0x3100 0x100>;
0316 interrupts = <43 2>;
0317 interrupt-parent = <&mpic>;
0318 dfsrr;
0319 };
0320
0321 dma@c300 {
0322 #address-cells = <1>;
0323 #size-cells = <1>;
0324 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
0325 reg = <0xc300 0x4>;
0326 ranges = <0x0 0xc100 0x200>;
0327 cell-index = <1>;
0328 dma-channel@0 {
0329 compatible = "fsl,mpc8572-dma-channel",
0330 "fsl,eloplus-dma-channel";
0331 reg = <0x0 0x80>;
0332 cell-index = <0>;
0333 interrupt-parent = <&mpic>;
0334 interrupts = <76 2>;
0335 };
0336 dma-channel@80 {
0337 compatible = "fsl,mpc8572-dma-channel",
0338 "fsl,eloplus-dma-channel";
0339 reg = <0x80 0x80>;
0340 cell-index = <1>;
0341 interrupt-parent = <&mpic>;
0342 interrupts = <77 2>;
0343 };
0344 dma-channel@100 {
0345 compatible = "fsl,mpc8572-dma-channel",
0346 "fsl,eloplus-dma-channel";
0347 reg = <0x100 0x80>;
0348 cell-index = <2>;
0349 interrupt-parent = <&mpic>;
0350 interrupts = <78 2>;
0351 };
0352 dma-channel@180 {
0353 compatible = "fsl,mpc8572-dma-channel",
0354 "fsl,eloplus-dma-channel";
0355 reg = <0x180 0x80>;
0356 cell-index = <3>;
0357 interrupt-parent = <&mpic>;
0358 interrupts = <79 2>;
0359 };
0360 };
0361
0362 dma@21300 {
0363 #address-cells = <1>;
0364 #size-cells = <1>;
0365 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
0366 reg = <0x21300 0x4>;
0367 ranges = <0x0 0x21100 0x200>;
0368 cell-index = <0>;
0369 dma-channel@0 {
0370 compatible = "fsl,mpc8572-dma-channel",
0371 "fsl,eloplus-dma-channel";
0372 reg = <0x0 0x80>;
0373 cell-index = <0>;
0374 interrupt-parent = <&mpic>;
0375 interrupts = <20 2>;
0376 };
0377 dma-channel@80 {
0378 compatible = "fsl,mpc8572-dma-channel",
0379 "fsl,eloplus-dma-channel";
0380 reg = <0x80 0x80>;
0381 cell-index = <1>;
0382 interrupt-parent = <&mpic>;
0383 interrupts = <21 2>;
0384 };
0385 dma-channel@100 {
0386 compatible = "fsl,mpc8572-dma-channel",
0387 "fsl,eloplus-dma-channel";
0388 reg = <0x100 0x80>;
0389 cell-index = <2>;
0390 interrupt-parent = <&mpic>;
0391 interrupts = <22 2>;
0392 };
0393 dma-channel@180 {
0394 compatible = "fsl,mpc8572-dma-channel",
0395 "fsl,eloplus-dma-channel";
0396 reg = <0x180 0x80>;
0397 cell-index = <3>;
0398 interrupt-parent = <&mpic>;
0399 interrupts = <23 2>;
0400 };
0401 };
0402
0403 /* eTSEC 1 */
0404 enet0: ethernet@24000 {
0405 #address-cells = <1>;
0406 #size-cells = <1>;
0407 cell-index = <0>;
0408 device_type = "network";
0409 model = "eTSEC";
0410 compatible = "gianfar";
0411 reg = <0x24000 0x1000>;
0412 ranges = <0x0 0x24000 0x1000>;
0413 local-mac-address = [ 00 00 00 00 00 00 ];
0414 interrupts = <29 2 30 2 34 2>;
0415 interrupt-parent = <&mpic>;
0416 tbi-handle = <&tbi0>;
0417 phy-handle = <&phy0>;
0418 phy-connection-type = "sgmii";
0419
0420 mdio@520 {
0421 #address-cells = <1>;
0422 #size-cells = <0>;
0423 compatible = "fsl,gianfar-mdio";
0424 reg = <0x520 0x20>;
0425
0426 phy0: ethernet-phy@1 {
0427 interrupt-parent = <&mpic>;
0428 interrupts = <8 1>;
0429 reg = <0x1>;
0430 };
0431 phy1: ethernet-phy@2 {
0432 interrupt-parent = <&mpic>;
0433 interrupts = <8 1>;
0434 reg = <0x2>;
0435 };
0436 tbi0: tbi-phy@11 {
0437 reg = <0x11>;
0438 device_type = "tbi-phy";
0439 };
0440 };
0441 };
0442
0443 /* eTSEC 2 */
0444 enet1: ethernet@25000 {
0445 #address-cells = <1>;
0446 #size-cells = <1>;
0447 cell-index = <1>;
0448 device_type = "network";
0449 model = "eTSEC";
0450 compatible = "gianfar";
0451 reg = <0x25000 0x1000>;
0452 ranges = <0x0 0x25000 0x1000>;
0453 local-mac-address = [ 00 00 00 00 00 00 ];
0454 interrupts = <35 2 36 2 40 2>;
0455 interrupt-parent = <&mpic>;
0456 tbi-handle = <&tbi1>;
0457 phy-handle = <&phy1>;
0458 phy-connection-type = "sgmii";
0459
0460 mdio@520 {
0461 #address-cells = <1>;
0462 #size-cells = <0>;
0463 compatible = "fsl,gianfar-tbi";
0464 reg = <0x520 0x20>;
0465
0466 tbi1: tbi-phy@11 {
0467 reg = <0x11>;
0468 device_type = "tbi-phy";
0469 };
0470 };
0471 };
0472
0473 /* UART0 */
0474 serial0: serial@4500 {
0475 cell-index = <0>;
0476 device_type = "serial";
0477 compatible = "fsl,ns16550", "ns16550";
0478 reg = <0x4500 0x100>;
0479 clock-frequency = <0>;
0480 interrupts = <42 2>;
0481 interrupt-parent = <&mpic>;
0482 };
0483
0484 /* UART1 */
0485 serial1: serial@4600 {
0486 cell-index = <1>;
0487 device_type = "serial";
0488 compatible = "fsl,ns16550", "ns16550";
0489 reg = <0x4600 0x100>;
0490 clock-frequency = <0>;
0491 interrupts = <42 2>;
0492 interrupt-parent = <&mpic>;
0493 };
0494
0495 global-utilities@e0000 { //global utilities block
0496 compatible = "fsl,mpc8572-guts";
0497 reg = <0xe0000 0x1000>;
0498 fsl,has-rstcr;
0499 };
0500
0501 msi@41600 {
0502 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
0503 reg = <0x41600 0x80>;
0504 msi-available-ranges = <0 0x100>;
0505 interrupts = <
0506 0xe0 0
0507 0xe1 0
0508 0xe2 0
0509 0xe3 0
0510 0xe4 0
0511 0xe5 0
0512 0xe6 0
0513 0xe7 0>;
0514 interrupt-parent = <&mpic>;
0515 };
0516
0517 crypto@30000 {
0518 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
0519 "fsl,sec2.1", "fsl,sec2.0";
0520 reg = <0x30000 0x10000>;
0521 interrupts = <45 2 58 2>;
0522 interrupt-parent = <&mpic>;
0523 fsl,num-channels = <4>;
0524 fsl,channel-fifo-len = <24>;
0525 fsl,exec-units-mask = <0x9fe>;
0526 fsl,descriptor-types-mask = <0x3ab0ebf>;
0527 };
0528
0529 mpic: pic@40000 {
0530 interrupt-controller;
0531 #address-cells = <0>;
0532 #interrupt-cells = <2>;
0533 reg = <0x40000 0x40000>;
0534 compatible = "chrp,open-pic";
0535 device_type = "open-pic";
0536 };
0537
0538 gpio0: gpio@f000 {
0539 compatible = "fsl,mpc8572-gpio";
0540 reg = <0xf000 0x1000>;
0541 interrupts = <47 2>;
0542 interrupt-parent = <&mpic>;
0543 #gpio-cells = <2>;
0544 gpio-controller;
0545 };
0546
0547 gpio-leds {
0548 compatible = "gpio-leds";
0549
0550 heartbeat {
0551 label = "Heartbeat";
0552 gpios = <&gpio0 4 1>;
0553 linux,default-trigger = "heartbeat";
0554 };
0555
0556 yellow {
0557 label = "Yellow";
0558 gpios = <&gpio0 5 1>;
0559 };
0560
0561 red {
0562 label = "Red";
0563 gpios = <&gpio0 6 1>;
0564 };
0565
0566 green {
0567 label = "Green";
0568 gpios = <&gpio0 7 1>;
0569 };
0570 };
0571
0572 /* PME (pattern-matcher) */
0573 pme@10000 {
0574 compatible = "fsl,mpc8572-pme", "pme8572";
0575 reg = <0x10000 0x5000>;
0576 interrupts = <57 2 64 2 65 2 66 2 67 2>;
0577 interrupt-parent = <&mpic>;
0578 };
0579
0580 tlu@2f000 {
0581 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
0582 reg = <0x2f000 0x1000>;
0583 interrupts = <61 2>;
0584 interrupt-parent = <&mpic>;
0585 };
0586
0587 tlu@15000 {
0588 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
0589 reg = <0x15000 0x1000>;
0590 interrupts = <75 2>;
0591 interrupt-parent = <&mpic>;
0592 };
0593 };
0594
0595 /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */
0596 pci0: pcie@ef008000 {
0597 compatible = "fsl,mpc8548-pcie";
0598 device_type = "pci";
0599 #interrupt-cells = <1>;
0600 #size-cells = <2>;
0601 #address-cells = <3>;
0602 reg = <0 0xef008000 0 0x1000>;
0603 bus-range = <0 255>;
0604 ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000
0605 0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>;
0606 clock-frequency = <33333333>;
0607 interrupt-parent = <&mpic>;
0608 interrupts = <24 2>;
0609 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
0610 interrupt-map = <
0611 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
0612 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
0613 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
0614 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
0615 >;
0616 pcie@0 {
0617 reg = <0x0 0x0 0x0 0x0 0x0>;
0618 #size-cells = <2>;
0619 #address-cells = <3>;
0620 device_type = "pci";
0621 ranges = <0x02000000 0x0 0xe0000000
0622 0x02000000 0x0 0xe0000000
0623 0x0 0x10000000
0624
0625 0x01000000 0x0 0x0
0626 0x01000000 0x0 0x0
0627 0x0 0x100000>;
0628 };
0629 };
0630
0631 /* PCI Express controller 2, PMC module via PEX8112 bridge */
0632 pci1: pcie@ef009000 {
0633 compatible = "fsl,mpc8548-pcie";
0634 device_type = "pci";
0635 #interrupt-cells = <1>;
0636 #size-cells = <2>;
0637 #address-cells = <3>;
0638 reg = <0 0xef009000 0 0x1000>;
0639 bus-range = <0 255>;
0640 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
0641 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>;
0642 clock-frequency = <33333333>;
0643 interrupt-parent = <&mpic>;
0644 interrupts = <25 2>;
0645 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0646 interrupt-map = <
0647 /* IDSEL 0x0 */
0648 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
0649 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
0650 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
0651 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
0652 >;
0653 pcie@0 {
0654 reg = <0x0 0x0 0x0 0x0 0x0>;
0655 #size-cells = <2>;
0656 #address-cells = <3>;
0657 device_type = "pci";
0658 ranges = <0x2000000 0x0 0xc0000000
0659 0x2000000 0x0 0xc0000000
0660 0x0 0x10000000
0661
0662 0x1000000 0x0 0x0
0663 0x1000000 0x0 0x0
0664 0x0 0x100000>;
0665 };
0666 };
0667
0668 /* PCI Express controller 1, XMC P15 */
0669 pci2: pcie@ef00a000 {
0670 compatible = "fsl,mpc8548-pcie";
0671 device_type = "pci";
0672 #interrupt-cells = <1>;
0673 #size-cells = <2>;
0674 #address-cells = <3>;
0675 reg = <0 0xef00a000 0 0x1000>;
0676 bus-range = <0 255>;
0677 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
0678 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
0679 clock-frequency = <33333333>;
0680 interrupt-parent = <&mpic>;
0681 interrupts = <26 2>;
0682 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0683 interrupt-map = <
0684 /* IDSEL 0x0 */
0685 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
0686 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
0687 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
0688 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
0689 >;
0690 pcie@0 {
0691 reg = <0x0 0x0 0x0 0x0 0x0>;
0692 #size-cells = <2>;
0693 #address-cells = <3>;
0694 device_type = "pci";
0695 ranges = <0x2000000 0x0 0x80000000
0696 0x2000000 0x0 0x80000000
0697 0x0 0x40000000
0698
0699 0x1000000 0x0 0x0
0700 0x1000000 0x0 0x0
0701 0x0 0x100000>;
0702 };
0703 };
0704 };
