0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
0004 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
0005 *
0006 * XPedite5301 PMC/XMC module based on MPC8572E
0007 */
0008
0009 /dts-v1/;
0010 / {
0011 model = "xes,xpedite5301";
0012 compatible = "xes,xpedite5301", "xes,MPC8572";
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015 form-factor = "PMC/XMC";
0016 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
0017
0018 aliases {
0019 ethernet0 = &enet0;
0020 ethernet1 = &enet1;
0021 serial0 = &serial0;
0022 serial1 = &serial1;
0023 pci1 = &pci1;
0024 pci2 = &pci2;
0025 };
0026
0027 cpus {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030
0031 PowerPC,8572@0 {
0032 device_type = "cpu";
0033 reg = <0x0>;
0034 d-cache-line-size = <32>; // 32 bytes
0035 i-cache-line-size = <32>; // 32 bytes
0036 d-cache-size = <0x8000>; // L1, 32K
0037 i-cache-size = <0x8000>; // L1, 32K
0038 timebase-frequency = <0>;
0039 bus-frequency = <0>;
0040 clock-frequency = <0>;
0041 next-level-cache = <&L2>;
0042 };
0043
0044 PowerPC,8572@1 {
0045 device_type = "cpu";
0046 reg = <0x1>;
0047 d-cache-line-size = <32>; // 32 bytes
0048 i-cache-line-size = <32>; // 32 bytes
0049 d-cache-size = <0x8000>; // L1, 32K
0050 i-cache-size = <0x8000>; // L1, 32K
0051 timebase-frequency = <0>;
0052 bus-frequency = <0>;
0053 clock-frequency = <0>;
0054 next-level-cache = <&L2>;
0055 };
0056 };
0057
0058 memory {
0059 device_type = "memory";
0060 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
0061 };
0062
0063 localbus@ef005000 {
0064 #address-cells = <2>;
0065 #size-cells = <1>;
0066 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
0067 reg = <0 0xef005000 0 0x1000>;
0068 interrupts = <19 2>;
0069 interrupt-parent = <&mpic>;
0070 /* Local bus region mappings */
0071 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
0072 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
0073 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
0074 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
0075
0076 nor-boot@0,0 {
0077 compatible = "amd,s29gl01gp", "cfi-flash";
0078 bank-width = <2>;
0079 reg = <0 0 0x8000000>; /* 128MB */
0080 #address-cells = <1>;
0081 #size-cells = <1>;
0082 partition@0 {
0083 label = "Primary user space";
0084 reg = <0x00000000 0x6f00000>; /* 111 MB */
0085 };
0086 partition@6f00000 {
0087 label = "Primary kernel";
0088 reg = <0x6f00000 0x1000000>; /* 16 MB */
0089 };
0090 partition@7f00000 {
0091 label = "Primary DTB";
0092 reg = <0x7f00000 0x40000>; /* 256 KB */
0093 };
0094 partition@7f40000 {
0095 label = "Primary U-Boot environment";
0096 reg = <0x7f40000 0x40000>; /* 256 KB */
0097 };
0098 partition@7f80000 {
0099 label = "Primary U-Boot";
0100 reg = <0x7f80000 0x80000>; /* 512 KB */
0101 read-only;
0102 };
0103 };
0104
0105 nor-alternate@1,0 {
0106 compatible = "amd,s29gl01gp", "cfi-flash";
0107 bank-width = <2>;
0108 //reg = <0xf0000000 0x08000000>; /* 128MB */
0109 reg = <1 0 0x8000000>; /* 128MB */
0110 #address-cells = <1>;
0111 #size-cells = <1>;
0112 partition@0 {
0113 label = "Secondary user space";
0114 reg = <0x00000000 0x6f00000>; /* 111 MB */
0115 };
0116 partition@6f00000 {
0117 label = "Secondary kernel";
0118 reg = <0x6f00000 0x1000000>; /* 16 MB */
0119 };
0120 partition@7f00000 {
0121 label = "Secondary DTB";
0122 reg = <0x7f00000 0x40000>; /* 256 KB */
0123 };
0124 partition@7f40000 {
0125 label = "Secondary U-Boot environment";
0126 reg = <0x7f40000 0x40000>; /* 256 KB */
0127 };
0128 partition@7f80000 {
0129 label = "Secondary U-Boot";
0130 reg = <0x7f80000 0x80000>; /* 512 KB */
0131 read-only;
0132 };
0133 };
0134
0135 nand@2,0 {
0136 #address-cells = <1>;
0137 #size-cells = <1>;
0138 /*
0139 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
0140 * Micron MT29F8G08DAA (2x 512 MB), or Micron
0141 * MT29F16G08FAA (2x 1 GB), depending on the build
0142 * configuration
0143 */
0144 compatible = "fsl,mpc8572-fcm-nand",
0145 "fsl,elbc-fcm-nand";
0146 reg = <2 0 0x40000>;
0147 /* U-Boot should fix this up if chip size > 1 GB */
0148 partition@0 {
0149 label = "NAND Filesystem";
0150 reg = <0 0x40000000>;
0151 };
0152 };
0153
0154 };
0155
0156 soc8572@ef000000 {
0157 #address-cells = <1>;
0158 #size-cells = <1>;
0159 device_type = "soc";
0160 compatible = "fsl,mpc8572-immr", "simple-bus";
0161 ranges = <0x0 0 0xef000000 0x100000>;
0162 bus-frequency = <0>; // Filled out by uboot.
0163
0164 ecm-law@0 {
0165 compatible = "fsl,ecm-law";
0166 reg = <0x0 0x1000>;
0167 fsl,num-laws = <12>;
0168 };
0169
0170 ecm@1000 {
0171 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
0172 reg = <0x1000 0x1000>;
0173 interrupts = <17 2>;
0174 interrupt-parent = <&mpic>;
0175 };
0176
0177 memory-controller@2000 {
0178 compatible = "fsl,mpc8572-memory-controller";
0179 reg = <0x2000 0x1000>;
0180 interrupt-parent = <&mpic>;
0181 interrupts = <18 2>;
0182 };
0183
0184 memory-controller@6000 {
0185 compatible = "fsl,mpc8572-memory-controller";
0186 reg = <0x6000 0x1000>;
0187 interrupt-parent = <&mpic>;
0188 interrupts = <18 2>;
0189 };
0190
0191 L2: l2-cache-controller@20000 {
0192 compatible = "fsl,mpc8572-l2-cache-controller";
0193 reg = <0x20000 0x1000>;
0194 cache-line-size = <32>; // 32 bytes
0195 cache-size = <0x100000>; // L2, 1M
0196 interrupt-parent = <&mpic>;
0197 interrupts = <16 2>;
0198 };
0199
0200 i2c@3000 {
0201 #address-cells = <1>;
0202 #size-cells = <0>;
0203 cell-index = <0>;
0204 compatible = "fsl-i2c";
0205 reg = <0x3000 0x100>;
0206 interrupts = <43 2>;
0207 interrupt-parent = <&mpic>;
0208 dfsrr;
0209
0210 temp-sensor@48 {
0211 compatible = "dallas,ds1631", "dallas,ds1621";
0212 reg = <0x48>;
0213 };
0214
0215 temp-sensor@4c {
0216 compatible = "adi,adt7461";
0217 reg = <0x4c>;
0218 };
0219
0220 cpu-supervisor@51 {
0221 compatible = "dallas,ds4510";
0222 reg = <0x51>;
0223 };
0224
0225 eeprom@54 {
0226 compatible = "atmel,at24c128b";
0227 reg = <0x54>;
0228 };
0229
0230 rtc@68 {
0231 compatible = "st,m41t00",
0232 "dallas,ds1338";
0233 reg = <0x68>;
0234 };
0235
0236 pcie-switch@70 {
0237 compatible = "plx,pex8518";
0238 reg = <0x70>;
0239 };
0240
0241 gpio1: gpio@18 {
0242 compatible = "nxp,pca9557";
0243 reg = <0x18>;
0244 #gpio-cells = <2>;
0245 gpio-controller;
0246 polarity = <0x00>;
0247 };
0248
0249 gpio2: gpio@1c {
0250 compatible = "nxp,pca9557";
0251 reg = <0x1c>;
0252 #gpio-cells = <2>;
0253 gpio-controller;
0254 polarity = <0x00>;
0255 };
0256
0257 gpio3: gpio@1e {
0258 compatible = "nxp,pca9557";
0259 reg = <0x1e>;
0260 #gpio-cells = <2>;
0261 gpio-controller;
0262 polarity = <0x00>;
0263 };
0264
0265 gpio4: gpio@1f {
0266 compatible = "nxp,pca9557";
0267 reg = <0x1f>;
0268 #gpio-cells = <2>;
0269 gpio-controller;
0270 polarity = <0x00>;
0271 };
0272 };
0273
0274 i2c@3100 {
0275 #address-cells = <1>;
0276 #size-cells = <0>;
0277 cell-index = <1>;
0278 compatible = "fsl-i2c";
0279 reg = <0x3100 0x100>;
0280 interrupts = <43 2>;
0281 interrupt-parent = <&mpic>;
0282 dfsrr;
0283 };
0284
0285 dma@c300 {
0286 #address-cells = <1>;
0287 #size-cells = <1>;
0288 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
0289 reg = <0xc300 0x4>;
0290 ranges = <0x0 0xc100 0x200>;
0291 cell-index = <1>;
0292 dma-channel@0 {
0293 compatible = "fsl,mpc8572-dma-channel",
0294 "fsl,eloplus-dma-channel";
0295 reg = <0x0 0x80>;
0296 cell-index = <0>;
0297 interrupt-parent = <&mpic>;
0298 interrupts = <76 2>;
0299 };
0300 dma-channel@80 {
0301 compatible = "fsl,mpc8572-dma-channel",
0302 "fsl,eloplus-dma-channel";
0303 reg = <0x80 0x80>;
0304 cell-index = <1>;
0305 interrupt-parent = <&mpic>;
0306 interrupts = <77 2>;
0307 };
0308 dma-channel@100 {
0309 compatible = "fsl,mpc8572-dma-channel",
0310 "fsl,eloplus-dma-channel";
0311 reg = <0x100 0x80>;
0312 cell-index = <2>;
0313 interrupt-parent = <&mpic>;
0314 interrupts = <78 2>;
0315 };
0316 dma-channel@180 {
0317 compatible = "fsl,mpc8572-dma-channel",
0318 "fsl,eloplus-dma-channel";
0319 reg = <0x180 0x80>;
0320 cell-index = <3>;
0321 interrupt-parent = <&mpic>;
0322 interrupts = <79 2>;
0323 };
0324 };
0325
0326 dma@21300 {
0327 #address-cells = <1>;
0328 #size-cells = <1>;
0329 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
0330 reg = <0x21300 0x4>;
0331 ranges = <0x0 0x21100 0x200>;
0332 cell-index = <0>;
0333 dma-channel@0 {
0334 compatible = "fsl,mpc8572-dma-channel",
0335 "fsl,eloplus-dma-channel";
0336 reg = <0x0 0x80>;
0337 cell-index = <0>;
0338 interrupt-parent = <&mpic>;
0339 interrupts = <20 2>;
0340 };
0341 dma-channel@80 {
0342 compatible = "fsl,mpc8572-dma-channel",
0343 "fsl,eloplus-dma-channel";
0344 reg = <0x80 0x80>;
0345 cell-index = <1>;
0346 interrupt-parent = <&mpic>;
0347 interrupts = <21 2>;
0348 };
0349 dma-channel@100 {
0350 compatible = "fsl,mpc8572-dma-channel",
0351 "fsl,eloplus-dma-channel";
0352 reg = <0x100 0x80>;
0353 cell-index = <2>;
0354 interrupt-parent = <&mpic>;
0355 interrupts = <22 2>;
0356 };
0357 dma-channel@180 {
0358 compatible = "fsl,mpc8572-dma-channel",
0359 "fsl,eloplus-dma-channel";
0360 reg = <0x180 0x80>;
0361 cell-index = <3>;
0362 interrupt-parent = <&mpic>;
0363 interrupts = <23 2>;
0364 };
0365 };
0366
0367 /* eTSEC 1 */
0368 enet0: ethernet@24000 {
0369 #address-cells = <1>;
0370 #size-cells = <1>;
0371 cell-index = <0>;
0372 device_type = "network";
0373 model = "eTSEC";
0374 compatible = "gianfar";
0375 reg = <0x24000 0x1000>;
0376 ranges = <0x0 0x24000 0x1000>;
0377 local-mac-address = [ 00 00 00 00 00 00 ];
0378 interrupts = <29 2 30 2 34 2>;
0379 interrupt-parent = <&mpic>;
0380 tbi-handle = <&tbi0>;
0381 phy-handle = <&phy0>;
0382 phy-connection-type = "sgmii";
0383
0384 mdio@520 {
0385 #address-cells = <1>;
0386 #size-cells = <0>;
0387 compatible = "fsl,gianfar-mdio";
0388 reg = <0x520 0x20>;
0389
0390 phy0: ethernet-phy@1 {
0391 interrupt-parent = <&mpic>;
0392 interrupts = <8 1>;
0393 reg = <0x1>;
0394 };
0395 phy1: ethernet-phy@2 {
0396 interrupt-parent = <&mpic>;
0397 interrupts = <8 1>;
0398 reg = <0x2>;
0399 };
0400 tbi0: tbi-phy@11 {
0401 reg = <0x11>;
0402 device_type = "tbi-phy";
0403 };
0404 };
0405 };
0406
0407 /* eTSEC 2 */
0408 enet1: ethernet@25000 {
0409 #address-cells = <1>;
0410 #size-cells = <1>;
0411 cell-index = <1>;
0412 device_type = "network";
0413 model = "eTSEC";
0414 compatible = "gianfar";
0415 reg = <0x25000 0x1000>;
0416 ranges = <0x0 0x25000 0x1000>;
0417 local-mac-address = [ 00 00 00 00 00 00 ];
0418 interrupts = <35 2 36 2 40 2>;
0419 interrupt-parent = <&mpic>;
0420 tbi-handle = <&tbi1>;
0421 phy-handle = <&phy1>;
0422 phy-connection-type = "sgmii";
0423
0424 mdio@520 {
0425 #address-cells = <1>;
0426 #size-cells = <0>;
0427 compatible = "fsl,gianfar-tbi";
0428 reg = <0x520 0x20>;
0429
0430 tbi1: tbi-phy@11 {
0431 reg = <0x11>;
0432 device_type = "tbi-phy";
0433 };
0434 };
0435 };
0436
0437 /* UART0 */
0438 serial0: serial@4500 {
0439 cell-index = <0>;
0440 device_type = "serial";
0441 compatible = "fsl,ns16550", "ns16550";
0442 reg = <0x4500 0x100>;
0443 clock-frequency = <0>;
0444 interrupts = <42 2>;
0445 interrupt-parent = <&mpic>;
0446 };
0447
0448 /* UART1 */
0449 serial1: serial@4600 {
0450 cell-index = <1>;
0451 device_type = "serial";
0452 compatible = "fsl,ns16550", "ns16550";
0453 reg = <0x4600 0x100>;
0454 clock-frequency = <0>;
0455 interrupts = <42 2>;
0456 interrupt-parent = <&mpic>;
0457 };
0458
0459 global-utilities@e0000 { //global utilities block
0460 compatible = "fsl,mpc8572-guts";
0461 reg = <0xe0000 0x1000>;
0462 fsl,has-rstcr;
0463 };
0464
0465 msi@41600 {
0466 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
0467 reg = <0x41600 0x80>;
0468 msi-available-ranges = <0 0x100>;
0469 interrupts = <
0470 0xe0 0
0471 0xe1 0
0472 0xe2 0
0473 0xe3 0
0474 0xe4 0
0475 0xe5 0
0476 0xe6 0
0477 0xe7 0>;
0478 interrupt-parent = <&mpic>;
0479 };
0480
0481 crypto@30000 {
0482 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
0483 "fsl,sec2.1", "fsl,sec2.0";
0484 reg = <0x30000 0x10000>;
0485 interrupts = <45 2 58 2>;
0486 interrupt-parent = <&mpic>;
0487 fsl,num-channels = <4>;
0488 fsl,channel-fifo-len = <24>;
0489 fsl,exec-units-mask = <0x9fe>;
0490 fsl,descriptor-types-mask = <0x3ab0ebf>;
0491 };
0492
0493 mpic: pic@40000 {
0494 interrupt-controller;
0495 #address-cells = <0>;
0496 #interrupt-cells = <2>;
0497 reg = <0x40000 0x40000>;
0498 compatible = "chrp,open-pic";
0499 device_type = "open-pic";
0500 };
0501
0502 gpio0: gpio@f000 {
0503 compatible = "fsl,mpc8572-gpio";
0504 reg = <0xf000 0x1000>;
0505 interrupts = <47 2>;
0506 interrupt-parent = <&mpic>;
0507 #gpio-cells = <2>;
0508 gpio-controller;
0509 };
0510
0511 gpio-leds {
0512 compatible = "gpio-leds";
0513
0514 heartbeat {
0515 label = "Heartbeat";
0516 gpios = <&gpio0 4 1>;
0517 linux,default-trigger = "heartbeat";
0518 };
0519
0520 yellow {
0521 label = "Yellow";
0522 gpios = <&gpio0 5 1>;
0523 };
0524
0525 red {
0526 label = "Red";
0527 gpios = <&gpio0 6 1>;
0528 };
0529
0530 green {
0531 label = "Green";
0532 gpios = <&gpio0 7 1>;
0533 };
0534 };
0535
0536 /* PME (pattern-matcher) */
0537 pme@10000 {
0538 compatible = "fsl,mpc8572-pme", "pme8572";
0539 reg = <0x10000 0x5000>;
0540 interrupts = <57 2 64 2 65 2 66 2 67 2>;
0541 interrupt-parent = <&mpic>;
0542 };
0543
0544 tlu@2f000 {
0545 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
0546 reg = <0x2f000 0x1000>;
0547 interrupts = <61 2>;
0548 interrupt-parent = <&mpic>;
0549 };
0550
0551 tlu@15000 {
0552 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
0553 reg = <0x15000 0x1000>;
0554 interrupts = <75 2>;
0555 interrupt-parent = <&mpic>;
0556 };
0557 };
0558
0559 /*
0560 * PCI Express controller 3 @ ef008000 is not used.
0561 * This would have been pci0 on other mpc85xx platforms.
0562 */
0563
0564 /* PCI Express controller 2, wired to XMC P15 connector */
0565 pci1: pcie@ef009000 {
0566 compatible = "fsl,mpc8548-pcie";
0567 device_type = "pci";
0568 #interrupt-cells = <1>;
0569 #size-cells = <2>;
0570 #address-cells = <3>;
0571 reg = <0 0xef009000 0 0x1000>;
0572 bus-range = <0 255>;
0573 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
0574 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
0575 clock-frequency = <33333333>;
0576 interrupt-parent = <&mpic>;
0577 interrupts = <25 2>;
0578 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0579 interrupt-map = <
0580 /* IDSEL 0x0 */
0581 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
0582 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
0583 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
0584 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
0585 >;
0586 pcie@0 {
0587 reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
0588 #size-cells = <2>;
0589 #address-cells = <3>;
0590 device_type = "pci";
0591 ranges = <0x2000000 0x0 0xc0000000
0592 0x2000000 0x0 0xc0000000
0593 0x0 0x10000000
0594
0595 0x1000000 0x0 0x0
0596 0x1000000 0x0 0x0
0597 0x0 0x100000>;
0598 };
0599 };
0600
0601 /* PCI Express controller 1, wired to PEX8112 for PMC interface */
0602 pci2: pcie@ef00a000 {
0603 compatible = "fsl,mpc8548-pcie";
0604 device_type = "pci";
0605 #interrupt-cells = <1>;
0606 #size-cells = <2>;
0607 #address-cells = <3>;
0608 reg = <0 0xef00a000 0 0x1000>;
0609 bus-range = <0 255>;
0610 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
0611 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
0612 clock-frequency = <33333333>;
0613 interrupt-parent = <&mpic>;
0614 interrupts = <26 2>;
0615 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0616 interrupt-map = <
0617 /* IDSEL 0x0 */
0618 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
0619 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
0620 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
0621 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
0622 >;
0623 pcie@0 {
0624 reg = <0x0 0x0 0x0 0x0 0x0>;
0625 #size-cells = <2>;
0626 #address-cells = <3>;
0627 device_type = "pci";
0628 ranges = <0x2000000 0x0 0x80000000
0629 0x2000000 0x0 0x80000000
0630 0x0 0x40000000
0631
0632 0x1000000 0x0 0x0
0633 0x1000000 0x0 0x0
0634 0x0 0x100000>;
0635 };
0636 };
0637 };
