0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
0004 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
0005 *
0006 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
0007 */
0008
0009 /dts-v1/;
0010 / {
0011 model = "xes,xcalibur1501";
0012 compatible = "xes,xcalibur1501", "xes,MPC8572";
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 aliases {
0017 ethernet0 = &enet0;
0018 ethernet1 = &enet1;
0019 ethernet2 = &enet2;
0020 ethernet3 = &enet3;
0021 serial0 = &serial0;
0022 serial1 = &serial1;
0023 pci2 = &pci2;
0024 };
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029
0030 PowerPC,8572@0 {
0031 device_type = "cpu";
0032 reg = <0x0>;
0033 d-cache-line-size = <32>; // 32 bytes
0034 i-cache-line-size = <32>; // 32 bytes
0035 d-cache-size = <0x8000>; // L1, 32K
0036 i-cache-size = <0x8000>; // L1, 32K
0037 timebase-frequency = <0>;
0038 bus-frequency = <0>;
0039 clock-frequency = <0>;
0040 next-level-cache = <&L2>;
0041 };
0042
0043 PowerPC,8572@1 {
0044 device_type = "cpu";
0045 reg = <0x1>;
0046 d-cache-line-size = <32>; // 32 bytes
0047 i-cache-line-size = <32>; // 32 bytes
0048 d-cache-size = <0x8000>; // L1, 32K
0049 i-cache-size = <0x8000>; // L1, 32K
0050 timebase-frequency = <0>;
0051 bus-frequency = <0>;
0052 clock-frequency = <0>;
0053 next-level-cache = <&L2>;
0054 };
0055 };
0056
0057 memory {
0058 device_type = "memory";
0059 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
0060 };
0061
0062 localbus@ef005000 {
0063 #address-cells = <2>;
0064 #size-cells = <1>;
0065 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
0066 reg = <0 0xef005000 0 0x1000>;
0067 interrupts = <19 2>;
0068 interrupt-parent = <&mpic>;
0069 /* Local bus region mappings */
0070 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */
0071 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */
0072 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
0073 3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */
0074 4 0 0 0xe9000000 0x100000>; /* CS4: USB */
0075
0076 nor-boot@0,0 {
0077 compatible = "amd,s29gl01gp", "cfi-flash";
0078 bank-width = <2>;
0079 reg = <0 0 0x8000000>; /* 128MB */
0080 #address-cells = <1>;
0081 #size-cells = <1>;
0082 partition@0 {
0083 label = "Primary user space";
0084 reg = <0x00000000 0x6f00000>; /* 111 MB */
0085 };
0086 partition@6f00000 {
0087 label = "Primary kernel";
0088 reg = <0x6f00000 0x1000000>; /* 16 MB */
0089 };
0090 partition@7f00000 {
0091 label = "Primary DTB";
0092 reg = <0x7f00000 0x40000>; /* 256 KB */
0093 };
0094 partition@7f40000 {
0095 label = "Primary U-Boot environment";
0096 reg = <0x7f40000 0x40000>; /* 256 KB */
0097 };
0098 partition@7f80000 {
0099 label = "Primary U-Boot";
0100 reg = <0x7f80000 0x80000>; /* 512 KB */
0101 read-only;
0102 };
0103 };
0104
0105 nor-alternate@1,0 {
0106 compatible = "amd,s29gl01gp", "cfi-flash";
0107 bank-width = <2>;
0108 //reg = <0xf0000000 0x08000000>; /* 128MB */
0109 reg = <1 0 0x8000000>; /* 128MB */
0110 #address-cells = <1>;
0111 #size-cells = <1>;
0112 partition@0 {
0113 label = "Secondary user space";
0114 reg = <0x00000000 0x6f00000>; /* 111 MB */
0115 };
0116 partition@6f00000 {
0117 label = "Secondary kernel";
0118 reg = <0x6f00000 0x1000000>; /* 16 MB */
0119 };
0120 partition@7f00000 {
0121 label = "Secondary DTB";
0122 reg = <0x7f00000 0x40000>; /* 256 KB */
0123 };
0124 partition@7f40000 {
0125 label = "Secondary U-Boot environment";
0126 reg = <0x7f40000 0x40000>; /* 256 KB */
0127 };
0128 partition@7f80000 {
0129 label = "Secondary U-Boot";
0130 reg = <0x7f80000 0x80000>; /* 512 KB */
0131 read-only;
0132 };
0133 };
0134
0135 nand@2,0 {
0136 #address-cells = <1>;
0137 #size-cells = <1>;
0138 /*
0139 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
0140 * Micron MT29F8G08DAA (2x 512 MB), or Micron
0141 * MT29F16G08FAA (2x 1 GB), depending on the build
0142 * configuration
0143 */
0144 compatible = "fsl,mpc8572-fcm-nand",
0145 "fsl,elbc-fcm-nand";
0146 reg = <2 0 0x40000>;
0147 /* U-Boot should fix this up if chip size > 1 GB */
0148 partition@0 {
0149 label = "NAND Filesystem";
0150 reg = <0 0x40000000>;
0151 };
0152 };
0153
0154 usb@4,0 {
0155 compatible = "nxp,usb-isp1761";
0156 reg = <4 0 0x100000>;
0157 bus-width = <32>;
0158 interrupt-parent = <&mpic>;
0159 interrupts = <10 1>;
0160 };
0161 };
0162
0163 soc8572@ef000000 {
0164 #address-cells = <1>;
0165 #size-cells = <1>;
0166 device_type = "soc";
0167 compatible = "fsl,mpc8572-immr", "simple-bus";
0168 ranges = <0x0 0 0xef000000 0x100000>;
0169 bus-frequency = <0>; // Filled out by uboot.
0170
0171 ecm-law@0 {
0172 compatible = "fsl,ecm-law";
0173 reg = <0x0 0x1000>;
0174 fsl,num-laws = <12>;
0175 };
0176
0177 ecm@1000 {
0178 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
0179 reg = <0x1000 0x1000>;
0180 interrupts = <17 2>;
0181 interrupt-parent = <&mpic>;
0182 };
0183
0184 memory-controller@2000 {
0185 compatible = "fsl,mpc8572-memory-controller";
0186 reg = <0x2000 0x1000>;
0187 interrupt-parent = <&mpic>;
0188 interrupts = <18 2>;
0189 };
0190
0191 memory-controller@6000 {
0192 compatible = "fsl,mpc8572-memory-controller";
0193 reg = <0x6000 0x1000>;
0194 interrupt-parent = <&mpic>;
0195 interrupts = <18 2>;
0196 };
0197
0198 L2: l2-cache-controller@20000 {
0199 compatible = "fsl,mpc8572-l2-cache-controller";
0200 reg = <0x20000 0x1000>;
0201 cache-line-size = <32>; // 32 bytes
0202 cache-size = <0x100000>; // L2, 1M
0203 interrupt-parent = <&mpic>;
0204 interrupts = <16 2>;
0205 };
0206
0207 i2c@3000 {
0208 #address-cells = <1>;
0209 #size-cells = <0>;
0210 cell-index = <0>;
0211 compatible = "fsl-i2c";
0212 reg = <0x3000 0x100>;
0213 interrupts = <43 2>;
0214 interrupt-parent = <&mpic>;
0215 dfsrr;
0216
0217 temp-sensor@48 {
0218 compatible = "dallas,ds1631", "dallas,ds1621";
0219 reg = <0x48>;
0220 };
0221
0222 temp-sensor@4c {
0223 compatible = "adi,adt7461";
0224 reg = <0x4c>;
0225 };
0226
0227 cpu-supervisor@51 {
0228 compatible = "dallas,ds4510";
0229 reg = <0x51>;
0230 };
0231
0232 eeprom@54 {
0233 compatible = "atmel,at24c128b";
0234 reg = <0x54>;
0235 };
0236
0237 rtc@68 {
0238 compatible = "st,m41t00",
0239 "dallas,ds1338";
0240 reg = <0x68>;
0241 };
0242
0243 pcie-switch@6a {
0244 compatible = "plx,pex8648";
0245 reg = <0x6a>;
0246 };
0247
0248 /* On-board signals for VID, flash, serial */
0249 gpio1: gpio@18 {
0250 compatible = "nxp,pca9557";
0251 reg = <0x18>;
0252 #gpio-cells = <2>;
0253 gpio-controller;
0254 polarity = <0x00>;
0255 };
0256
0257 /* PMC0/XMC0 signals */
0258 gpio2: gpio@1c {
0259 compatible = "nxp,pca9557";
0260 reg = <0x1c>;
0261 #gpio-cells = <2>;
0262 gpio-controller;
0263 polarity = <0x00>;
0264 };
0265
0266 /* PMC1/XMC1 signals */
0267 gpio3: gpio@1d {
0268 compatible = "nxp,pca9557";
0269 reg = <0x1d>;
0270 #gpio-cells = <2>;
0271 gpio-controller;
0272 polarity = <0x00>;
0273 };
0274
0275 /* CompactPCI signals (sysen, GA[4:0]) */
0276 gpio4: gpio@1e {
0277 compatible = "nxp,pca9557";
0278 reg = <0x1e>;
0279 #gpio-cells = <2>;
0280 gpio-controller;
0281 polarity = <0x00>;
0282 };
0283
0284 /* CompactPCI J5 GPIO and FAL/DEG/PRST */
0285 gpio5: gpio@1f {
0286 compatible = "nxp,pca9557";
0287 reg = <0x1f>;
0288 #gpio-cells = <2>;
0289 gpio-controller;
0290 polarity = <0x00>;
0291 };
0292 };
0293
0294 i2c@3100 {
0295 #address-cells = <1>;
0296 #size-cells = <0>;
0297 cell-index = <1>;
0298 compatible = "fsl-i2c";
0299 reg = <0x3100 0x100>;
0300 interrupts = <43 2>;
0301 interrupt-parent = <&mpic>;
0302 dfsrr;
0303 };
0304
0305 dma@c300 {
0306 #address-cells = <1>;
0307 #size-cells = <1>;
0308 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
0309 reg = <0xc300 0x4>;
0310 ranges = <0x0 0xc100 0x200>;
0311 cell-index = <1>;
0312 dma-channel@0 {
0313 compatible = "fsl,mpc8572-dma-channel",
0314 "fsl,eloplus-dma-channel";
0315 reg = <0x0 0x80>;
0316 cell-index = <0>;
0317 interrupt-parent = <&mpic>;
0318 interrupts = <76 2>;
0319 };
0320 dma-channel@80 {
0321 compatible = "fsl,mpc8572-dma-channel",
0322 "fsl,eloplus-dma-channel";
0323 reg = <0x80 0x80>;
0324 cell-index = <1>;
0325 interrupt-parent = <&mpic>;
0326 interrupts = <77 2>;
0327 };
0328 dma-channel@100 {
0329 compatible = "fsl,mpc8572-dma-channel",
0330 "fsl,eloplus-dma-channel";
0331 reg = <0x100 0x80>;
0332 cell-index = <2>;
0333 interrupt-parent = <&mpic>;
0334 interrupts = <78 2>;
0335 };
0336 dma-channel@180 {
0337 compatible = "fsl,mpc8572-dma-channel",
0338 "fsl,eloplus-dma-channel";
0339 reg = <0x180 0x80>;
0340 cell-index = <3>;
0341 interrupt-parent = <&mpic>;
0342 interrupts = <79 2>;
0343 };
0344 };
0345
0346 dma@21300 {
0347 #address-cells = <1>;
0348 #size-cells = <1>;
0349 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
0350 reg = <0x21300 0x4>;
0351 ranges = <0x0 0x21100 0x200>;
0352 cell-index = <0>;
0353 dma-channel@0 {
0354 compatible = "fsl,mpc8572-dma-channel",
0355 "fsl,eloplus-dma-channel";
0356 reg = <0x0 0x80>;
0357 cell-index = <0>;
0358 interrupt-parent = <&mpic>;
0359 interrupts = <20 2>;
0360 };
0361 dma-channel@80 {
0362 compatible = "fsl,mpc8572-dma-channel",
0363 "fsl,eloplus-dma-channel";
0364 reg = <0x80 0x80>;
0365 cell-index = <1>;
0366 interrupt-parent = <&mpic>;
0367 interrupts = <21 2>;
0368 };
0369 dma-channel@100 {
0370 compatible = "fsl,mpc8572-dma-channel",
0371 "fsl,eloplus-dma-channel";
0372 reg = <0x100 0x80>;
0373 cell-index = <2>;
0374 interrupt-parent = <&mpic>;
0375 interrupts = <22 2>;
0376 };
0377 dma-channel@180 {
0378 compatible = "fsl,mpc8572-dma-channel",
0379 "fsl,eloplus-dma-channel";
0380 reg = <0x180 0x80>;
0381 cell-index = <3>;
0382 interrupt-parent = <&mpic>;
0383 interrupts = <23 2>;
0384 };
0385 };
0386
0387 /* eTSEC 1 front panel 0 */
0388 enet0: ethernet@24000 {
0389 #address-cells = <1>;
0390 #size-cells = <1>;
0391 cell-index = <0>;
0392 device_type = "network";
0393 model = "eTSEC";
0394 compatible = "gianfar";
0395 reg = <0x24000 0x1000>;
0396 ranges = <0x0 0x24000 0x1000>;
0397 local-mac-address = [ 00 00 00 00 00 00 ];
0398 interrupts = <29 2 30 2 34 2>;
0399 interrupt-parent = <&mpic>;
0400 tbi-handle = <&tbi0>;
0401 phy-handle = <&phy0>;
0402 phy-connection-type = "sgmii";
0403
0404 mdio@520 {
0405 #address-cells = <1>;
0406 #size-cells = <0>;
0407 compatible = "fsl,gianfar-mdio";
0408 reg = <0x520 0x20>;
0409
0410 phy0: ethernet-phy@1 {
0411 interrupt-parent = <&mpic>;
0412 interrupts = <4 1>;
0413 reg = <0x1>;
0414 };
0415 phy1: ethernet-phy@2 {
0416 interrupt-parent = <&mpic>;
0417 interrupts = <4 1>;
0418 reg = <0x2>;
0419 };
0420 phy2: ethernet-phy@3 {
0421 interrupt-parent = <&mpic>;
0422 interrupts = <5 1>;
0423 reg = <0x3>;
0424 };
0425 phy3: ethernet-phy@4 {
0426 interrupt-parent = <&mpic>;
0427 interrupts = <5 1>;
0428 reg = <0x4>;
0429 };
0430 tbi0: tbi-phy@11 {
0431 reg = <0x11>;
0432 device_type = "tbi-phy";
0433 };
0434 };
0435 };
0436
0437 /* eTSEC 2 front panel 1 */
0438 enet1: ethernet@25000 {
0439 #address-cells = <1>;
0440 #size-cells = <1>;
0441 cell-index = <1>;
0442 device_type = "network";
0443 model = "eTSEC";
0444 compatible = "gianfar";
0445 reg = <0x25000 0x1000>;
0446 ranges = <0x0 0x25000 0x1000>;
0447 local-mac-address = [ 00 00 00 00 00 00 ];
0448 interrupts = <35 2 36 2 40 2>;
0449 interrupt-parent = <&mpic>;
0450 tbi-handle = <&tbi1>;
0451 phy-handle = <&phy1>;
0452 phy-connection-type = "sgmii";
0453
0454 mdio@520 {
0455 #address-cells = <1>;
0456 #size-cells = <0>;
0457 compatible = "fsl,gianfar-tbi";
0458 reg = <0x520 0x20>;
0459
0460 tbi1: tbi-phy@11 {
0461 reg = <0x11>;
0462 device_type = "tbi-phy";
0463 };
0464 };
0465 };
0466
0467 /* eTSEC 3 PICMG2.16 backplane port 0 */
0468 enet2: ethernet@26000 {
0469 #address-cells = <1>;
0470 #size-cells = <1>;
0471 cell-index = <2>;
0472 device_type = "network";
0473 model = "eTSEC";
0474 compatible = "gianfar";
0475 reg = <0x26000 0x1000>;
0476 ranges = <0x0 0x26000 0x1000>;
0477 local-mac-address = [ 00 00 00 00 00 00 ];
0478 interrupts = <31 2 32 2 33 2>;
0479 interrupt-parent = <&mpic>;
0480 tbi-handle = <&tbi2>;
0481 phy-handle = <&phy2>;
0482 phy-connection-type = "sgmii";
0483
0484 mdio@520 {
0485 #address-cells = <1>;
0486 #size-cells = <0>;
0487 compatible = "fsl,gianfar-tbi";
0488 reg = <0x520 0x20>;
0489
0490 tbi2: tbi-phy@11 {
0491 reg = <0x11>;
0492 device_type = "tbi-phy";
0493 };
0494 };
0495 };
0496
0497 /* eTSEC 4 PICMG2.16 backplane port 1 */
0498 enet3: ethernet@27000 {
0499 #address-cells = <1>;
0500 #size-cells = <1>;
0501 cell-index = <3>;
0502 device_type = "network";
0503 model = "eTSEC";
0504 compatible = "gianfar";
0505 reg = <0x27000 0x1000>;
0506 ranges = <0x0 0x27000 0x1000>;
0507 local-mac-address = [ 00 00 00 00 00 00 ];
0508 interrupts = <37 2 38 2 39 2>;
0509 interrupt-parent = <&mpic>;
0510 tbi-handle = <&tbi3>;
0511 phy-handle = <&phy3>;
0512 phy-connection-type = "sgmii";
0513
0514 mdio@520 {
0515 #address-cells = <1>;
0516 #size-cells = <0>;
0517 compatible = "fsl,gianfar-tbi";
0518 reg = <0x520 0x20>;
0519
0520 tbi3: tbi-phy@11 {
0521 reg = <0x11>;
0522 device_type = "tbi-phy";
0523 };
0524 };
0525 };
0526
0527 /* UART0 */
0528 serial0: serial@4500 {
0529 cell-index = <0>;
0530 device_type = "serial";
0531 compatible = "fsl,ns16550", "ns16550";
0532 reg = <0x4500 0x100>;
0533 clock-frequency = <0>;
0534 interrupts = <42 2>;
0535 interrupt-parent = <&mpic>;
0536 };
0537
0538 /* UART1 */
0539 serial1: serial@4600 {
0540 cell-index = <1>;
0541 device_type = "serial";
0542 compatible = "fsl,ns16550", "ns16550";
0543 reg = <0x4600 0x100>;
0544 clock-frequency = <0>;
0545 interrupts = <42 2>;
0546 interrupt-parent = <&mpic>;
0547 };
0548
0549 global-utilities@e0000 { //global utilities block
0550 compatible = "fsl,mpc8572-guts";
0551 reg = <0xe0000 0x1000>;
0552 fsl,has-rstcr;
0553 };
0554
0555 msi@41600 {
0556 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
0557 reg = <0x41600 0x80>;
0558 msi-available-ranges = <0 0x100>;
0559 interrupts = <
0560 0xe0 0
0561 0xe1 0
0562 0xe2 0
0563 0xe3 0
0564 0xe4 0
0565 0xe5 0
0566 0xe6 0
0567 0xe7 0>;
0568 interrupt-parent = <&mpic>;
0569 };
0570
0571 crypto@30000 {
0572 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
0573 "fsl,sec2.1", "fsl,sec2.0";
0574 reg = <0x30000 0x10000>;
0575 interrupts = <45 2 58 2>;
0576 interrupt-parent = <&mpic>;
0577 fsl,num-channels = <4>;
0578 fsl,channel-fifo-len = <24>;
0579 fsl,exec-units-mask = <0x9fe>;
0580 fsl,descriptor-types-mask = <0x3ab0ebf>;
0581 };
0582
0583 mpic: pic@40000 {
0584 interrupt-controller;
0585 #address-cells = <0>;
0586 #interrupt-cells = <2>;
0587 reg = <0x40000 0x40000>;
0588 compatible = "chrp,open-pic";
0589 device_type = "open-pic";
0590 };
0591
0592 gpio0: gpio@f000 {
0593 compatible = "fsl,mpc8572-gpio";
0594 reg = <0xf000 0x1000>;
0595 interrupts = <47 2>;
0596 interrupt-parent = <&mpic>;
0597 #gpio-cells = <2>;
0598 gpio-controller;
0599 };
0600
0601 gpio-leds {
0602 compatible = "gpio-leds";
0603
0604 heartbeat {
0605 label = "Heartbeat";
0606 gpios = <&gpio0 4 1>;
0607 linux,default-trigger = "heartbeat";
0608 };
0609
0610 yellow {
0611 label = "Yellow";
0612 gpios = <&gpio0 5 1>;
0613 };
0614
0615 red {
0616 label = "Red";
0617 gpios = <&gpio0 6 1>;
0618 };
0619
0620 green {
0621 label = "Green";
0622 gpios = <&gpio0 7 1>;
0623 };
0624 };
0625
0626 /* PME (pattern-matcher) */
0627 pme@10000 {
0628 compatible = "fsl,mpc8572-pme", "pme8572";
0629 reg = <0x10000 0x5000>;
0630 interrupts = <57 2 64 2 65 2 66 2 67 2>;
0631 interrupt-parent = <&mpic>;
0632 };
0633
0634 tlu@2f000 {
0635 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
0636 reg = <0x2f000 0x1000>;
0637 interrupts = <61 2>;
0638 interrupt-parent = <&mpic>;
0639 };
0640
0641 tlu@15000 {
0642 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
0643 reg = <0x15000 0x1000>;
0644 interrupts = <75 2>;
0645 interrupt-parent = <&mpic>;
0646 };
0647 };
0648
0649 /*
0650 * PCI Express controller 3 @ ef008000 is not used.
0651 * This would have been pci0 on other mpc85xx platforms.
0652 *
0653 * PCI Express controller 2 @ ef009000 is not used.
0654 * This would have been pci1 on other mpc85xx platforms.
0655 */
0656
0657 /* PCI Express controller 1, wired to PEX8648 PCIe switch */
0658 pci2: pcie@ef00a000 {
0659 compatible = "fsl,mpc8548-pcie";
0660 device_type = "pci";
0661 #interrupt-cells = <1>;
0662 #size-cells = <2>;
0663 #address-cells = <3>;
0664 reg = <0 0xef00a000 0 0x1000>;
0665 bus-range = <0 255>;
0666 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
0667 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
0668 clock-frequency = <33333333>;
0669 interrupt-parent = <&mpic>;
0670 interrupts = <26 2>;
0671 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0672 interrupt-map = <
0673 /* IDSEL 0x0 */
0674 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
0675 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
0676 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
0677 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
0678 >;
0679 pcie@0 {
0680 reg = <0x0 0x0 0x0 0x0 0x0>;
0681 #size-cells = <2>;
0682 #address-cells = <3>;
0683 device_type = "pci";
0684 ranges = <0x2000000 0x0 0x80000000
0685 0x2000000 0x0 0x80000000
0686 0x0 0x40000000
0687
0688 0x1000000 0x0 0x0
0689 0x1000000 0x0 0x0
0690 0x0 0x100000>;
0691 };
0692 };
0693 };
