0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Turris 1.x Device Tree Source
0004 *
0005 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
0006 *
0007 * Pinout, Schematics and Altium hardware design files are open source
0008 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
0009 */
0010
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/interrupt-controller/irq.h>
0013 #include <dt-bindings/leds/common.h>
0014 /include/ "fsl/p2020si-pre.dtsi"
0015
0016 / {
0017 model = "Turris 1.x";
0018 compatible = "cznic,turris1x", "fsl,P2020RDB-PC"; /* fsl,P2020RDB-PC is required for booting Linux */
0019
0020 aliases {
0021 ethernet0 = &enet0;
0022 ethernet1 = &enet1;
0023 ethernet2 = &enet2;
0024 serial0 = &serial0;
0025 serial1 = &serial1;
0026 pci0 = &pci0;
0027 pci1 = &pci1;
0028 pci2 = &pci2;
0029 spi0 = &spi0;
0030 };
0031
0032 memory {
0033 device_type = "memory";
0034 };
0035
0036 soc: soc@ffe00000 {
0037 ranges = <0x0 0x0 0xffe00000 0x00100000>;
0038
0039 i2c@3000 {
0040 /* PCA9557PW GPIO controller for boot config */
0041 gpio-controller@18 {
0042 compatible = "nxp,pca9557";
0043 label = "bootcfg";
0044 reg = <0x18>;
0045 #gpio-cells = <2>;
0046 gpio-controller;
0047 polarity = <0x00>;
0048 };
0049
0050 /* STM32F030R8T6 MCU for power control */
0051 power-control@2a {
0052 /*
0053 * Turris Power Control firmware runs on STM32F0 MCU.
0054 * This firmware is open source and available at:
0055 * https://gitlab.nic.cz/turris/hw/turris_power_control
0056 */
0057 reg = <0x2a>;
0058 };
0059
0060 /* DDR3 SPD/EEPROM PSWP instruction */
0061 eeprom@32 {
0062 reg = <0x32>;
0063 };
0064
0065 /* SA56004ED temperature control */
0066 temperature-sensor@4c {
0067 compatible = "nxp,sa56004";
0068 reg = <0x4c>;
0069 interrupt-parent = <&gpio>;
0070 interrupts = <12 IRQ_TYPE_LEVEL_LOW>, /* GPIO12 - ALERT pin */
0071 <13 IRQ_TYPE_LEVEL_LOW>; /* GPIO13 - CRIT pin */
0072 };
0073
0074 /* DDR3 SPD/EEPROM */
0075 eeprom@52 {
0076 compatible = "atmel,spd";
0077 reg = <0x52>;
0078 };
0079
0080 /* MCP79402-I/ST Protected EEPROM */
0081 eeprom@57 {
0082 reg = <0x57>;
0083 };
0084
0085 /* ATSHA204-TH-DA-T crypto module */
0086 crypto@64 {
0087 compatible = "atmel,atsha204";
0088 reg = <0x64>;
0089 };
0090
0091 /* IDT6V49205BNLGI clock generator */
0092 clock-generator@69 {
0093 compatible = "idt,6v49205b";
0094 reg = <0x69>;
0095 };
0096
0097 /* MCP79402-I/ST RTC */
0098 rtc@6f {
0099 compatible = "microchip,mcp7940x";
0100 reg = <0x6f>;
0101 interrupt-parent = <&gpio>;
0102 interrupts = <14 0>; /* GPIO14 - MFP pin */
0103 };
0104 };
0105
0106 /* SPI on connector P1 */
0107 spi0: spi@7000 {
0108 };
0109
0110 gpio: gpio-controller@fc00 {
0111 #interrupt-cells = <2>;
0112 interrupt-controller;
0113 };
0114
0115 /* Connected to SMSC USB2412-DZK 2-Port USB 2.0 Hub Controller */
0116 usb@22000 {
0117 phy_type = "ulpi";
0118 dr_mode = "host";
0119 };
0120
0121 enet0: ethernet@24000 {
0122 /* Connected to port 6 of QCA8337N-AL3C switch */
0123 phy-connection-type = "rgmii-id";
0124
0125 fixed-link {
0126 speed = <1000>;
0127 full-duplex;
0128 };
0129 };
0130
0131 mdio@24520 {
0132 /* KSZ9031RNXCA ethernet phy for WAN port */
0133 phy: ethernet-phy@7 {
0134 interrupts = <3 1 0 0>;
0135 reg = <0x7>;
0136 };
0137
0138 /* QCA8337N-AL3C switch with integrated ethernet PHYs for LAN ports */
0139 switch@10 {
0140 compatible = "qca,qca8337";
0141 interrupts = <2 1 0 0>;
0142 reg = <0x10>;
0143
0144 ports {
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147
0148 port@0 {
0149 reg = <0>;
0150 label = "cpu1";
0151 ethernet = <&enet1>;
0152 phy-mode = "rgmii-id";
0153
0154 fixed-link {
0155 speed = <1000>;
0156 full-duplex;
0157 };
0158 };
0159
0160 port@1 {
0161 reg = <1>;
0162 label = "lan5";
0163 };
0164
0165 port@2 {
0166 reg = <2>;
0167 label = "lan4";
0168 };
0169
0170 port@3 {
0171 reg = <3>;
0172 label = "lan3";
0173 };
0174
0175 port@4 {
0176 reg = <4>;
0177 label = "lan2";
0178 };
0179
0180 port@5 {
0181 reg = <5>;
0182 label = "lan1";
0183 };
0184
0185 port@6 {
0186 reg = <6>;
0187 label = "cpu0";
0188 ethernet = <&enet0>;
0189 phy-mode = "rgmii-id";
0190
0191 fixed-link {
0192 speed = <1000>;
0193 full-duplex;
0194 };
0195 };
0196 };
0197 };
0198 };
0199
0200 ptp_clock@24e00 {
0201 fsl,tclk-period = <5>;
0202 fsl,tmr-prsc = <200>;
0203 fsl,tmr-add = <0xcccccccd>;
0204 fsl,tmr-fiper1 = <0x3b9ac9fb>;
0205 fsl,tmr-fiper2 = <0x0001869b>;
0206 fsl,max-adj = <249999999>;
0207 };
0208
0209 enet1: ethernet@25000 {
0210 /* Connected to port 0 of QCA8337N-AL3C switch */
0211 phy-connection-type = "rgmii-id";
0212
0213 fixed-link {
0214 speed = <1000>;
0215 full-duplex;
0216 };
0217 };
0218
0219 mdio@25520 {
0220 status = "disabled";
0221 };
0222
0223 enet2: ethernet@26000 {
0224 /* Connected to KSZ9031RNXCA ethernet phy (WAN port) */
0225 label = "wan";
0226 phy-handle = <&phy>;
0227 phy-connection-type = "rgmii-id";
0228 };
0229
0230 mdio@26520 {
0231 status = "disabled";
0232 };
0233
0234 sdhc@2e000 {
0235 bus-width = <4>;
0236 cd-gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
0237 };
0238 };
0239
0240 lbc: localbus@ffe05000 {
0241 reg = <0 0xffe05000 0 0x1000>;
0242
0243 ranges = <0x0 0x0 0x0 0xef000000 0x01000000>, /* NOR */
0244 <0x1 0x0 0x0 0xff800000 0x00040000>, /* NAND */
0245 <0x3 0x0 0x0 0xffa00000 0x00020000>; /* CPLD */
0246
0247 /* S29GL128P90TFIR10 NOR */
0248 nor@0,0 {
0249 compatible = "cfi-flash";
0250 reg = <0x0 0x0 0x01000000>;
0251 bank-width = <2>;
0252 device-width = <1>;
0253
0254 partitions {
0255 compatible = "fixed-partitions";
0256 #address-cells = <1>;
0257 #size-cells = <1>;
0258
0259 partition@0 {
0260 /* 128 kB for Device Tree Blob */
0261 reg = <0x00000000 0x00020000>;
0262 label = "dtb";
0263 };
0264
0265 partition@20000 {
0266 /* 1.7 MB for Rescue Linux Kernel Image */
0267 reg = <0x00020000 0x001a0000>;
0268 label = "rescue-kernel";
0269 };
0270
0271 partition@1c0000 {
0272 /* 1.5 MB for Rescue JFFS2 Root File System */
0273 reg = <0x001c0000 0x00180000>;
0274 label = "rescue-rootfs";
0275 };
0276
0277 partition@340000 {
0278 /* 11 MB for TAR.XZ Backup with content of NAND Root File System */
0279 reg = <0x00340000 0x00b00000>;
0280 label = "backup-rootfs";
0281 };
0282
0283 partition@e40000 {
0284 /* 768 kB for Certificates JFFS2 File System */
0285 reg = <0x00e40000 0x000c0000>;
0286 label = "certificates";
0287 };
0288
0289 /* free unused space 0x00f00000-0x00f20000 */
0290
0291 partition@f20000 {
0292 /* 128 kB for U-Boot Environment Variables */
0293 reg = <0x00f20000 0x00020000>;
0294 label = "u-boot-env";
0295 };
0296
0297 partition@f40000 {
0298 /* 768 kB for U-Boot Bootloader Image */
0299 reg = <0x00f40000 0x000c0000>;
0300 label = "u-boot";
0301 };
0302 };
0303 };
0304
0305 /* MT29F2G08ABAEAWP:E NAND */
0306 nand@1,0 {
0307 compatible = "fsl,p2020-fcm-nand", "fsl,elbc-fcm-nand";
0308 reg = <0x1 0x0 0x00040000>;
0309 nand-ecc-mode = "soft";
0310 nand-ecc-algo = "bch";
0311
0312 partitions {
0313 compatible = "fixed-partitions";
0314 #address-cells = <1>;
0315 #size-cells = <1>;
0316
0317 partition@0 {
0318 /* 256 MB for UBI with one volume: UBIFS Root File System */
0319 reg = <0x00000000 0x10000000>;
0320 label = "rootfs";
0321 };
0322 };
0323 };
0324
0325 /* LCMXO1200C-3FTN256C FPGA */
0326 cpld@3,0 {
0327 /*
0328 * Turris CPLD firmware which runs on this Lattice FPGA,
0329 * is extended version of P1021RDB-PC CPLD v4.1 firmware.
0330 * It is backward compatible with its original version
0331 * and the only extension is support for Turris LEDs.
0332 * Turris CPLD firmware is open source and available at:
0333 * https://gitlab.nic.cz/turris/hw/turris_cpld/-/blob/master/CZ_NIC_Router_CPLD.v
0334 */
0335 compatible = "cznic,turris1x-cpld", "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
0336 reg = <0x3 0x0 0x30>;
0337 #address-cells = <1>;
0338 #size-cells = <1>;
0339 ranges = <0x0 0x3 0x0 0x00020000>;
0340
0341 /* MAX6370KA+T watchdog */
0342 watchdog@2 {
0343 /*
0344 * CPLD firmware maps SET0, SET1 and SET2
0345 * input logic of MAX6370KA+T chip to CPLD
0346 * memory space at byte offset 0x2. WDI
0347 * input logic is outside of the CPLD and
0348 * connected via external GPIO.
0349 */
0350 compatible = "maxim,max6370";
0351 reg = <0x02 0x01>;
0352 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
0353 };
0354
0355 reboot@d {
0356 compatible = "syscon-reboot";
0357 reg = <0x0d 0x01>;
0358 offset = <0x0d>;
0359 mask = <0x01>;
0360 value = <0x01>;
0361 };
0362
0363 led-controller@13 {
0364 /*
0365 * LEDs are controlled by CPLD firmware.
0366 * All five LAN LEDs share common RGB settings
0367 * and so it is not possible to set different
0368 * colors on different LAN ports.
0369 */
0370 compatible = "cznic,turris1x-leds";
0371 reg = <0x13 0x1d>;
0372 #address-cells = <1>;
0373 #size-cells = <0>;
0374
0375 multi-led@0 {
0376 reg = <0x0>;
0377 color = <LED_COLOR_ID_RGB>;
0378 function = LED_FUNCTION_WAN;
0379 };
0380
0381 multi-led@1 {
0382 reg = <0x1>;
0383 color = <LED_COLOR_ID_RGB>;
0384 function = LED_FUNCTION_LAN;
0385 function-enumerator = <5>;
0386 };
0387
0388 multi-led@2 {
0389 reg = <0x2>;
0390 color = <LED_COLOR_ID_RGB>;
0391 function = LED_FUNCTION_LAN;
0392 function-enumerator = <4>;
0393 };
0394
0395 multi-led@3 {
0396 reg = <0x3>;
0397 color = <LED_COLOR_ID_RGB>;
0398 function = LED_FUNCTION_LAN;
0399 function-enumerator = <3>;
0400 };
0401
0402 multi-led@4 {
0403 reg = <0x4>;
0404 color = <LED_COLOR_ID_RGB>;
0405 function = LED_FUNCTION_LAN;
0406 function-enumerator = <2>;
0407 };
0408
0409 multi-led@5 {
0410 reg = <0x5>;
0411 color = <LED_COLOR_ID_RGB>;
0412 function = LED_FUNCTION_LAN;
0413 function-enumerator = <1>;
0414 };
0415
0416 multi-led@6 {
0417 reg = <0x6>;
0418 color = <LED_COLOR_ID_RGB>;
0419 function = LED_FUNCTION_WLAN;
0420 };
0421
0422 multi-led@7 {
0423 reg = <0x7>;
0424 color = <LED_COLOR_ID_RGB>;
0425 function = LED_FUNCTION_POWER;
0426 };
0427 };
0428 };
0429 };
0430
0431 pci2: pcie@ffe08000 {
0432 /*
0433 * PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller.
0434 * This xHCI controller is available only on Turris 1.1 boards.
0435 * Turris 1.0 boards have nothing connected to this PCIe bus,
0436 * so system would see only PCIe Root Port of this PCIe Root
0437 * Complex. TUSB7340RKM xHCI controller has four SuperSpeed
0438 * channels. Channel 0 is connected to the front USB 3.0 port,
0439 * channel 1 (but only USB 2.0 subset) to USB 2.0 pins on mPCIe
0440 * slot 1 (CN5), channels 2 and 3 to connector P600.
0441 *
0442 * P2020 PCIe Root Port uses 1MB of PCIe MEM and xHCI controller
0443 * uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required.
0444 * So allocate 2MB of PCIe MEM for this PCIe bus.
0445 */
0446 reg = <0 0xffe08000 0 0x1000>;
0447 ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00200000>, /* MEM */
0448 <0x01000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; /* IO */
0449
0450 pcie@0 {
0451 ranges;
0452 };
0453 };
0454
0455 pci1: pcie@ffe09000 {
0456 /* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */
0457 reg = <0 0xffe09000 0 0x1000>;
0458 ranges = <0x02000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000>, /* MEM */
0459 <0x01000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; /* IO */
0460
0461 pcie@0 {
0462 ranges;
0463 };
0464 };
0465
0466 pci0: pcie@ffe0a000 {
0467 /*
0468 * PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card.
0469 * Turris 1.1 boards have in this mPCIe slot additional USB 2.0
0470 * pins via channel 1 of TUSB7340RKM xHCI controller and also
0471 * additional SIM card slot, both for USB-based WWAN cards.
0472 */
0473 reg = <0 0xffe0a000 0 0x1000>;
0474 ranges = <0x02000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000>, /* MEM */
0475 <0x01000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; /* IO */
0476
0477 pcie@0 {
0478 ranges;
0479 };
0480 };
0481 };
0482
0483 /include/ "fsl/p2020si-post.dtsi"
