0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * TQM 8555 Device Tree Source
0004 *
0005 * Copyright 2008 Freescale Semiconductor Inc.
0006 */
0007
0008 /dts-v1/;
0009
0010 / {
0011 model = "tqc,tqm8555";
0012 compatible = "tqc,tqm8555";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 aliases {
0017 ethernet0 = &enet0;
0018 ethernet1 = &enet1;
0019 serial0 = &serial0;
0020 serial1 = &serial1;
0021 pci0 = &pci0;
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 PowerPC,8555@0 {
0029 device_type = "cpu";
0030 reg = <0>;
0031 d-cache-line-size = <32>;
0032 i-cache-line-size = <32>;
0033 d-cache-size = <32768>;
0034 i-cache-size = <32768>;
0035 timebase-frequency = <0>;
0036 bus-frequency = <0>;
0037 clock-frequency = <0>;
0038 next-level-cache = <&L2>;
0039 };
0040 };
0041
0042 memory {
0043 device_type = "memory";
0044 reg = <0x00000000 0x10000000>;
0045 };
0046
0047 soc@e0000000 {
0048 #address-cells = <1>;
0049 #size-cells = <1>;
0050 device_type = "soc";
0051 ranges = <0x0 0xe0000000 0x100000>;
0052 bus-frequency = <0>;
0053 compatible = "fsl,mpc8555-immr", "simple-bus";
0054
0055 ecm-law@0 {
0056 compatible = "fsl,ecm-law";
0057 reg = <0x0 0x1000>;
0058 fsl,num-laws = <8>;
0059 };
0060
0061 ecm@1000 {
0062 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
0063 reg = <0x1000 0x1000>;
0064 interrupts = <17 2>;
0065 interrupt-parent = <&mpic>;
0066 };
0067
0068 memory-controller@2000 {
0069 compatible = "fsl,mpc8540-memory-controller";
0070 reg = <0x2000 0x1000>;
0071 interrupt-parent = <&mpic>;
0072 interrupts = <18 2>;
0073 };
0074
0075 L2: l2-cache-controller@20000 {
0076 compatible = "fsl,mpc8540-l2-cache-controller";
0077 reg = <0x20000 0x1000>;
0078 cache-line-size = <32>;
0079 cache-size = <0x40000>; // L2, 256K
0080 interrupt-parent = <&mpic>;
0081 interrupts = <16 2>;
0082 };
0083
0084 i2c@3000 {
0085 #address-cells = <1>;
0086 #size-cells = <0>;
0087 cell-index = <0>;
0088 compatible = "fsl-i2c";
0089 reg = <0x3000 0x100>;
0090 interrupts = <43 2>;
0091 interrupt-parent = <&mpic>;
0092 dfsrr;
0093
0094 dtt@48 {
0095 compatible = "national,lm75";
0096 reg = <0x48>;
0097 };
0098
0099 rtc@68 {
0100 compatible = "dallas,ds1337";
0101 reg = <0x68>;
0102 };
0103 };
0104
0105 dma@21300 {
0106 #address-cells = <1>;
0107 #size-cells = <1>;
0108 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
0109 reg = <0x21300 0x4>;
0110 ranges = <0x0 0x21100 0x200>;
0111 cell-index = <0>;
0112 dma-channel@0 {
0113 compatible = "fsl,mpc8555-dma-channel",
0114 "fsl,eloplus-dma-channel";
0115 reg = <0x0 0x80>;
0116 cell-index = <0>;
0117 interrupt-parent = <&mpic>;
0118 interrupts = <20 2>;
0119 };
0120 dma-channel@80 {
0121 compatible = "fsl,mpc8555-dma-channel",
0122 "fsl,eloplus-dma-channel";
0123 reg = <0x80 0x80>;
0124 cell-index = <1>;
0125 interrupt-parent = <&mpic>;
0126 interrupts = <21 2>;
0127 };
0128 dma-channel@100 {
0129 compatible = "fsl,mpc8555-dma-channel",
0130 "fsl,eloplus-dma-channel";
0131 reg = <0x100 0x80>;
0132 cell-index = <2>;
0133 interrupt-parent = <&mpic>;
0134 interrupts = <22 2>;
0135 };
0136 dma-channel@180 {
0137 compatible = "fsl,mpc8555-dma-channel",
0138 "fsl,eloplus-dma-channel";
0139 reg = <0x180 0x80>;
0140 cell-index = <3>;
0141 interrupt-parent = <&mpic>;
0142 interrupts = <23 2>;
0143 };
0144 };
0145
0146 enet0: ethernet@24000 {
0147 #address-cells = <1>;
0148 #size-cells = <1>;
0149 cell-index = <0>;
0150 device_type = "network";
0151 model = "TSEC";
0152 compatible = "gianfar";
0153 reg = <0x24000 0x1000>;
0154 ranges = <0x0 0x24000 0x1000>;
0155 local-mac-address = [ 00 00 00 00 00 00 ];
0156 interrupts = <29 2 30 2 34 2>;
0157 interrupt-parent = <&mpic>;
0158 tbi-handle = <&tbi0>;
0159 phy-handle = <&phy2>;
0160
0161 mdio@520 {
0162 #address-cells = <1>;
0163 #size-cells = <0>;
0164 compatible = "fsl,gianfar-mdio";
0165 reg = <0x520 0x20>;
0166
0167 phy1: ethernet-phy@1 {
0168 interrupt-parent = <&mpic>;
0169 interrupts = <8 1>;
0170 reg = <1>;
0171 };
0172 phy2: ethernet-phy@2 {
0173 interrupt-parent = <&mpic>;
0174 interrupts = <8 1>;
0175 reg = <2>;
0176 };
0177 phy3: ethernet-phy@3 {
0178 interrupt-parent = <&mpic>;
0179 interrupts = <8 1>;
0180 reg = <3>;
0181 };
0182 tbi0: tbi-phy@11 {
0183 reg = <0x11>;
0184 device_type = "tbi-phy";
0185 };
0186 };
0187 };
0188
0189 enet1: ethernet@25000 {
0190 #address-cells = <1>;
0191 #size-cells = <1>;
0192 cell-index = <1>;
0193 device_type = "network";
0194 model = "TSEC";
0195 compatible = "gianfar";
0196 reg = <0x25000 0x1000>;
0197 ranges = <0x0 0x25000 0x1000>;
0198 local-mac-address = [ 00 00 00 00 00 00 ];
0199 interrupts = <35 2 36 2 40 2>;
0200 interrupt-parent = <&mpic>;
0201 tbi-handle = <&tbi1>;
0202 phy-handle = <&phy1>;
0203
0204 mdio@520 {
0205 #address-cells = <1>;
0206 #size-cells = <0>;
0207 compatible = "fsl,gianfar-tbi";
0208 reg = <0x520 0x20>;
0209
0210 tbi1: tbi-phy@11 {
0211 reg = <0x11>;
0212 device_type = "tbi-phy";
0213 };
0214 };
0215 };
0216
0217 serial0: serial@4500 {
0218 cell-index = <0>;
0219 device_type = "serial";
0220 compatible = "fsl,ns16550", "ns16550";
0221 reg = <0x4500 0x100>; // reg base, size
0222 clock-frequency = <0>; // should we fill in in uboot?
0223 interrupts = <42 2>;
0224 interrupt-parent = <&mpic>;
0225 };
0226
0227 serial1: serial@4600 {
0228 cell-index = <1>;
0229 device_type = "serial";
0230 compatible = "fsl,ns16550", "ns16550";
0231 reg = <0x4600 0x100>; // reg base, size
0232 clock-frequency = <0>; // should we fill in in uboot?
0233 interrupts = <42 2>;
0234 interrupt-parent = <&mpic>;
0235 };
0236
0237 crypto@30000 {
0238 compatible = "fsl,sec2.0";
0239 reg = <0x30000 0x10000>;
0240 interrupts = <45 2>;
0241 interrupt-parent = <&mpic>;
0242 fsl,num-channels = <4>;
0243 fsl,channel-fifo-len = <24>;
0244 fsl,exec-units-mask = <0x7e>;
0245 fsl,descriptor-types-mask = <0x01010ebf>;
0246 };
0247
0248 mpic: pic@40000 {
0249 interrupt-controller;
0250 #address-cells = <0>;
0251 #interrupt-cells = <2>;
0252 reg = <0x40000 0x40000>;
0253 device_type = "open-pic";
0254 compatible = "chrp,open-pic";
0255 };
0256
0257 cpm@919c0 {
0258 #address-cells = <1>;
0259 #size-cells = <1>;
0260 compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus";
0261 reg = <0x919c0 0x30>;
0262 ranges;
0263
0264 muram@80000 {
0265 #address-cells = <1>;
0266 #size-cells = <1>;
0267 ranges = <0 0x80000 0x10000>;
0268
0269 data@0 {
0270 compatible = "fsl,cpm-muram-data";
0271 reg = <0 0x2000 0x9000 0x1000>;
0272 };
0273 };
0274
0275 brg@919f0 {
0276 compatible = "fsl,mpc8555-brg",
0277 "fsl,cpm2-brg",
0278 "fsl,cpm-brg";
0279 reg = <0x919f0 0x10 0x915f0 0x10>;
0280 clock-frequency = <0>;
0281 };
0282
0283 cpmpic: pic@90c00 {
0284 interrupt-controller;
0285 #address-cells = <0>;
0286 #interrupt-cells = <2>;
0287 interrupts = <46 2>;
0288 interrupt-parent = <&mpic>;
0289 reg = <0x90c00 0x80>;
0290 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
0291 };
0292 };
0293 };
0294
0295 pci0: pci@e0008000 {
0296 #interrupt-cells = <1>;
0297 #size-cells = <2>;
0298 #address-cells = <3>;
0299 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
0300 device_type = "pci";
0301 reg = <0xe0008000 0x1000>;
0302 clock-frequency = <66666666>;
0303 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0304 interrupt-map = <
0305 /* IDSEL 28 */
0306 0xe000 0 0 1 &mpic 2 1
0307 0xe000 0 0 2 &mpic 3 1
0308 0xe000 0 0 3 &mpic 6 1
0309 0xe000 0 0 4 &mpic 5 1
0310
0311 /* IDSEL 11 */
0312 0x5800 0 0 1 &mpic 6 1
0313 0x5800 0 0 2 &mpic 5 1
0314 >;
0315
0316 interrupt-parent = <&mpic>;
0317 interrupts = <24 2>;
0318 bus-range = <0 0>;
0319 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
0320 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
0321 };
0322 };
