0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * TQM8548 Device Tree Source
0004 *
0005 * Copyright 2006 Freescale Semiconductor Inc.
0006 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
0007 */
0008
0009 /dts-v1/;
0010
0011 / {
0012 model = "tqc,tqm8548";
0013 compatible = "tqc,tqm8548";
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016
0017 aliases {
0018 ethernet0 = &enet0;
0019 ethernet1 = &enet1;
0020 ethernet2 = &enet2;
0021 ethernet3 = &enet3;
0022
0023 serial0 = &serial0;
0024 serial1 = &serial1;
0025 pci0 = &pci0;
0026 pci1 = &pci1;
0027 };
0028
0029 cpus {
0030 #address-cells = <1>;
0031 #size-cells = <0>;
0032
0033 PowerPC,8548@0 {
0034 device_type = "cpu";
0035 reg = <0>;
0036 d-cache-line-size = <32>; // 32 bytes
0037 i-cache-line-size = <32>; // 32 bytes
0038 d-cache-size = <0x8000>; // L1, 32K
0039 i-cache-size = <0x8000>; // L1, 32K
0040 next-level-cache = <&L2>;
0041 };
0042 };
0043
0044 memory {
0045 device_type = "memory";
0046 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
0047 };
0048
0049 soc@e0000000 {
0050 #address-cells = <1>;
0051 #size-cells = <1>;
0052 device_type = "soc";
0053 ranges = <0x0 0xe0000000 0x100000>;
0054 bus-frequency = <0>;
0055 compatible = "fsl,mpc8548-immr", "simple-bus";
0056
0057 ecm-law@0 {
0058 compatible = "fsl,ecm-law";
0059 reg = <0x0 0x1000>;
0060 fsl,num-laws = <10>;
0061 };
0062
0063 ecm@1000 {
0064 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
0065 reg = <0x1000 0x1000>;
0066 interrupts = <17 2>;
0067 interrupt-parent = <&mpic>;
0068 };
0069
0070 memory-controller@2000 {
0071 compatible = "fsl,mpc8548-memory-controller";
0072 reg = <0x2000 0x1000>;
0073 interrupt-parent = <&mpic>;
0074 interrupts = <18 2>;
0075 };
0076
0077 L2: l2-cache-controller@20000 {
0078 compatible = "fsl,mpc8548-l2-cache-controller";
0079 reg = <0x20000 0x1000>;
0080 cache-line-size = <32>; // 32 bytes
0081 cache-size = <0x80000>; // L2, 512K
0082 interrupt-parent = <&mpic>;
0083 interrupts = <16 2>;
0084 };
0085
0086 i2c@3000 {
0087 #address-cells = <1>;
0088 #size-cells = <0>;
0089 cell-index = <0>;
0090 compatible = "fsl-i2c";
0091 reg = <0x3000 0x100>;
0092 interrupts = <43 2>;
0093 interrupt-parent = <&mpic>;
0094 dfsrr;
0095
0096 dtt@48 {
0097 compatible = "national,lm75";
0098 reg = <0x48>;
0099 };
0100
0101 rtc@68 {
0102 compatible = "dallas,ds1337";
0103 reg = <0x68>;
0104 };
0105 };
0106
0107 i2c@3100 {
0108 #address-cells = <1>;
0109 #size-cells = <0>;
0110 cell-index = <1>;
0111 compatible = "fsl-i2c";
0112 reg = <0x3100 0x100>;
0113 interrupts = <43 2>;
0114 interrupt-parent = <&mpic>;
0115 dfsrr;
0116 };
0117
0118 dma@21300 {
0119 #address-cells = <1>;
0120 #size-cells = <1>;
0121 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
0122 reg = <0x21300 0x4>;
0123 ranges = <0x0 0x21100 0x200>;
0124 cell-index = <0>;
0125 dma-channel@0 {
0126 compatible = "fsl,mpc8548-dma-channel",
0127 "fsl,eloplus-dma-channel";
0128 reg = <0x0 0x80>;
0129 cell-index = <0>;
0130 interrupt-parent = <&mpic>;
0131 interrupts = <20 2>;
0132 };
0133 dma-channel@80 {
0134 compatible = "fsl,mpc8548-dma-channel",
0135 "fsl,eloplus-dma-channel";
0136 reg = <0x80 0x80>;
0137 cell-index = <1>;
0138 interrupt-parent = <&mpic>;
0139 interrupts = <21 2>;
0140 };
0141 dma-channel@100 {
0142 compatible = "fsl,mpc8548-dma-channel",
0143 "fsl,eloplus-dma-channel";
0144 reg = <0x100 0x80>;
0145 cell-index = <2>;
0146 interrupt-parent = <&mpic>;
0147 interrupts = <22 2>;
0148 };
0149 dma-channel@180 {
0150 compatible = "fsl,mpc8548-dma-channel",
0151 "fsl,eloplus-dma-channel";
0152 reg = <0x180 0x80>;
0153 cell-index = <3>;
0154 interrupt-parent = <&mpic>;
0155 interrupts = <23 2>;
0156 };
0157 };
0158
0159 enet0: ethernet@24000 {
0160 #address-cells = <1>;
0161 #size-cells = <1>;
0162 cell-index = <0>;
0163 device_type = "network";
0164 model = "eTSEC";
0165 compatible = "gianfar";
0166 reg = <0x24000 0x1000>;
0167 ranges = <0x0 0x24000 0x1000>;
0168 local-mac-address = [ 00 00 00 00 00 00 ];
0169 interrupts = <29 2 30 2 34 2>;
0170 interrupt-parent = <&mpic>;
0171 tbi-handle = <&tbi0>;
0172 phy-handle = <&phy2>;
0173
0174 mdio@520 {
0175 #address-cells = <1>;
0176 #size-cells = <0>;
0177 compatible = "fsl,gianfar-mdio";
0178 reg = <0x520 0x20>;
0179
0180 phy1: ethernet-phy@0 {
0181 interrupt-parent = <&mpic>;
0182 interrupts = <8 1>;
0183 reg = <1>;
0184 };
0185 phy2: ethernet-phy@1 {
0186 interrupt-parent = <&mpic>;
0187 interrupts = <8 1>;
0188 reg = <2>;
0189 };
0190 phy3: ethernet-phy@3 {
0191 interrupt-parent = <&mpic>;
0192 interrupts = <8 1>;
0193 reg = <3>;
0194 };
0195 phy4: ethernet-phy@4 {
0196 interrupt-parent = <&mpic>;
0197 interrupts = <8 1>;
0198 reg = <4>;
0199 };
0200 phy5: ethernet-phy@5 {
0201 interrupt-parent = <&mpic>;
0202 interrupts = <8 1>;
0203 reg = <5>;
0204 };
0205 tbi0: tbi-phy@11 {
0206 reg = <0x11>;
0207 device_type = "tbi-phy";
0208 };
0209 };
0210 };
0211
0212 enet1: ethernet@25000 {
0213 #address-cells = <1>;
0214 #size-cells = <1>;
0215 cell-index = <1>;
0216 device_type = "network";
0217 model = "eTSEC";
0218 compatible = "gianfar";
0219 reg = <0x25000 0x1000>;
0220 ranges = <0x0 0x25000 0x1000>;
0221 local-mac-address = [ 00 00 00 00 00 00 ];
0222 interrupts = <35 2 36 2 40 2>;
0223 interrupt-parent = <&mpic>;
0224 tbi-handle = <&tbi1>;
0225 phy-handle = <&phy1>;
0226
0227 mdio@520 {
0228 #address-cells = <1>;
0229 #size-cells = <0>;
0230 compatible = "fsl,gianfar-tbi";
0231 reg = <0x520 0x20>;
0232
0233 tbi1: tbi-phy@11 {
0234 reg = <0x11>;
0235 device_type = "tbi-phy";
0236 };
0237 };
0238 };
0239
0240 enet2: ethernet@26000 {
0241 #address-cells = <1>;
0242 #size-cells = <1>;
0243 cell-index = <2>;
0244 device_type = "network";
0245 model = "eTSEC";
0246 compatible = "gianfar";
0247 reg = <0x26000 0x1000>;
0248 ranges = <0x0 0x26000 0x1000>;
0249 local-mac-address = [ 00 00 00 00 00 00 ];
0250 interrupts = <31 2 32 2 33 2>;
0251 interrupt-parent = <&mpic>;
0252 tbi-handle = <&tbi2>;
0253 phy-handle = <&phy4>;
0254
0255 mdio@520 {
0256 #address-cells = <1>;
0257 #size-cells = <0>;
0258 compatible = "fsl,gianfar-tbi";
0259 reg = <0x520 0x20>;
0260
0261 tbi2: tbi-phy@11 {
0262 reg = <0x11>;
0263 device_type = "tbi-phy";
0264 };
0265 };
0266 };
0267
0268 enet3: ethernet@27000 {
0269 #address-cells = <1>;
0270 #size-cells = <1>;
0271 cell-index = <3>;
0272 device_type = "network";
0273 model = "eTSEC";
0274 compatible = "gianfar";
0275 reg = <0x27000 0x1000>;
0276 ranges = <0x0 0x27000 0x1000>;
0277 local-mac-address = [ 00 00 00 00 00 00 ];
0278 interrupts = <37 2 38 2 39 2>;
0279 interrupt-parent = <&mpic>;
0280 tbi-handle = <&tbi3>;
0281 phy-handle = <&phy5>;
0282
0283 mdio@520 {
0284 #address-cells = <1>;
0285 #size-cells = <0>;
0286 compatible = "fsl,gianfar-tbi";
0287 reg = <0x520 0x20>;
0288
0289 tbi3: tbi-phy@11 {
0290 reg = <0x11>;
0291 device_type = "tbi-phy";
0292 };
0293 };
0294 };
0295
0296 serial0: serial@4500 {
0297 cell-index = <0>;
0298 device_type = "serial";
0299 compatible = "fsl,ns16550", "ns16550";
0300 reg = <0x4500 0x100>; // reg base, size
0301 clock-frequency = <0>; // should we fill in in uboot?
0302 current-speed = <115200>;
0303 interrupts = <42 2>;
0304 interrupt-parent = <&mpic>;
0305 };
0306
0307 serial1: serial@4600 {
0308 cell-index = <1>;
0309 device_type = "serial";
0310 compatible = "fsl,ns16550", "ns16550";
0311 reg = <0x4600 0x100>; // reg base, size
0312 clock-frequency = <0>; // should we fill in in uboot?
0313 current-speed = <115200>;
0314 interrupts = <42 2>;
0315 interrupt-parent = <&mpic>;
0316 };
0317
0318 global-utilities@e0000 { // global utilities reg
0319 compatible = "fsl,mpc8548-guts";
0320 reg = <0xe0000 0x1000>;
0321 fsl,has-rstcr;
0322 };
0323
0324 mpic: pic@40000 {
0325 interrupt-controller;
0326 #address-cells = <0>;
0327 #interrupt-cells = <2>;
0328 reg = <0x40000 0x40000>;
0329 compatible = "chrp,open-pic";
0330 device_type = "open-pic";
0331 };
0332 };
0333
0334 localbus@e0005000 {
0335 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
0336 "simple-bus";
0337 #address-cells = <2>;
0338 #size-cells = <1>;
0339 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
0340 interrupt-parent = <&mpic>;
0341 interrupts = <19 2>;
0342
0343 ranges = <
0344 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
0345 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
0346 2 0x0 0xe3000000 0x00008000 // CAN (2 x CC770)
0347 3 0x0 0xe3010000 0x00008000 // NAND FLASH
0348
0349 >;
0350
0351 flash@1,0 {
0352 #address-cells = <1>;
0353 #size-cells = <1>;
0354 compatible = "cfi-flash";
0355 reg = <1 0x0 0x8000000>;
0356 bank-width = <4>;
0357 device-width = <1>;
0358
0359 partition@0 {
0360 label = "kernel";
0361 reg = <0x00000000 0x00200000>;
0362 };
0363 partition@200000 {
0364 label = "root";
0365 reg = <0x00200000 0x00300000>;
0366 };
0367 partition@500000 {
0368 label = "user";
0369 reg = <0x00500000 0x07a00000>;
0370 };
0371 partition@7f00000 {
0372 label = "env1";
0373 reg = <0x07f00000 0x00040000>;
0374 };
0375 partition@7f40000 {
0376 label = "env2";
0377 reg = <0x07f40000 0x00040000>;
0378 };
0379 partition@7f80000 {
0380 label = "u-boot";
0381 reg = <0x07f80000 0x00080000>;
0382 read-only;
0383 };
0384 };
0385
0386 /* Note: CAN support needs be enabled in U-Boot */
0387 can@2,0 {
0388 compatible = "bosch,cc770"; // Bosch CC770
0389 reg = <2 0x0 0x100>;
0390 interrupts = <4 1>;
0391 interrupt-parent = <&mpic>;
0392 bosch,external-clock-frequency = <16000000>;
0393 bosch,disconnect-rx1-input;
0394 bosch,disconnect-tx1-output;
0395 bosch,iso-low-speed-mux;
0396 bosch,clock-out-frequency = <16000000>;
0397 };
0398
0399 can@2,100 {
0400 compatible = "bosch,cc770"; // Bosch CC770
0401 reg = <2 0x100 0x100>;
0402 interrupts = <4 1>;
0403 interrupt-parent = <&mpic>;
0404 bosch,external-clock-frequency = <16000000>;
0405 bosch,disconnect-rx1-input;
0406 bosch,disconnect-tx1-output;
0407 bosch,iso-low-speed-mux;
0408 };
0409
0410 /* Note: NAND support needs to be enabled in U-Boot */
0411 upm@3,0 {
0412 #address-cells = <0>;
0413 #size-cells = <0>;
0414 compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
0415 reg = <3 0x0 0x800>;
0416 fsl,upm-addr-offset = <0x10>;
0417 fsl,upm-cmd-offset = <0x08>;
0418 /* Micron MT29F8G08FAB multi-chip device */
0419 fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
0420 fsl,upm-wait-flags = <0x5>;
0421 chip-delay = <25>; // in micro-seconds
0422
0423 nand@0 {
0424 #address-cells = <1>;
0425 #size-cells = <1>;
0426
0427 partition@0 {
0428 label = "fs";
0429 reg = <0x00000000 0x10000000>;
0430 };
0431 };
0432 };
0433 };
0434
0435 pci0: pci@e0008000 {
0436 #interrupt-cells = <1>;
0437 #size-cells = <2>;
0438 #address-cells = <3>;
0439 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
0440 device_type = "pci";
0441 reg = <0xe0008000 0x1000>;
0442 clock-frequency = <33333333>;
0443 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0444 interrupt-map = <
0445 /* IDSEL 28 */
0446 0xe000 0 0 1 &mpic 2 1
0447 0xe000 0 0 2 &mpic 3 1
0448 0xe000 0 0 3 &mpic 6 1
0449 0xe000 0 0 4 &mpic 5 1
0450
0451 /* IDSEL 11 */
0452 0x5800 0 0 1 &mpic 6 1
0453 0x5800 0 0 2 &mpic 5 1
0454 >;
0455
0456 interrupt-parent = <&mpic>;
0457 interrupts = <24 2>;
0458 bus-range = <0 0>;
0459 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
0460 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
0461 };
0462
0463 pci1: pcie@e000a000 {
0464 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0465 interrupt-map = <
0466 /* IDSEL 0x0 (PEX) */
0467 0x00000 0 0 1 &mpic 0 1
0468 0x00000 0 0 2 &mpic 1 1
0469 0x00000 0 0 3 &mpic 2 1
0470 0x00000 0 0 4 &mpic 3 1>;
0471
0472 interrupt-parent = <&mpic>;
0473 interrupts = <26 2>;
0474 bus-range = <0 0xff>;
0475 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000
0476 0x01000000 0 0x00000000 0xef000000 0 0x08000000>;
0477 clock-frequency = <33333333>;
0478 #interrupt-cells = <1>;
0479 #size-cells = <2>;
0480 #address-cells = <3>;
0481 reg = <0xe000a000 0x1000>;
0482 compatible = "fsl,mpc8548-pcie";
0483 device_type = "pci";
0484 pcie@0 {
0485 reg = <0 0 0 0 0>;
0486 #size-cells = <2>;
0487 #address-cells = <3>;
0488 device_type = "pci";
0489 ranges = <0x02000000 0 0xc0000000 0x02000000 0
0490 0xc0000000 0 0x20000000
0491 0x01000000 0 0x00000000 0x01000000 0
0492 0x00000000 0 0x08000000>;
0493 };
0494 };
0495 };
