0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * TQM5200 board Device Tree Source
0004 *
0005 * Copyright (C) 2007 Semihalf
0006 * Marian Balakowicz <m8@semihalf.com>
0007 */
0008
0009 /dts-v1/;
0010
0011 / {
0012 model = "tqc,tqm5200";
0013 compatible = "tqc,tqm5200";
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016 interrupt-parent = <&mpc5200_pic>;
0017
0018 cpus {
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021
0022 PowerPC,5200@0 {
0023 device_type = "cpu";
0024 reg = <0>;
0025 d-cache-line-size = <32>;
0026 i-cache-line-size = <32>;
0027 d-cache-size = <0x4000>; // L1, 16K
0028 i-cache-size = <0x4000>; // L1, 16K
0029 timebase-frequency = <0>; // from bootloader
0030 bus-frequency = <0>; // from bootloader
0031 clock-frequency = <0>; // from bootloader
0032 };
0033 };
0034
0035 memory@0 {
0036 device_type = "memory";
0037 reg = <0x00000000 0x04000000>; // 64MB
0038 };
0039
0040 soc5200@f0000000 {
0041 #address-cells = <1>;
0042 #size-cells = <1>;
0043 compatible = "fsl,mpc5200-immr";
0044 ranges = <0 0xf0000000 0x0000c000>;
0045 reg = <0xf0000000 0x00000100>;
0046 bus-frequency = <0>; // from bootloader
0047 system-frequency = <0>; // from bootloader
0048
0049 cdm@200 {
0050 compatible = "fsl,mpc5200-cdm";
0051 reg = <0x200 0x38>;
0052 };
0053
0054 mpc5200_pic: interrupt-controller@500 {
0055 // 5200 interrupts are encoded into two levels;
0056 interrupt-controller;
0057 #interrupt-cells = <3>;
0058 compatible = "fsl,mpc5200-pic";
0059 reg = <0x500 0x80>;
0060 };
0061
0062 timer@600 { // General Purpose Timer
0063 compatible = "fsl,mpc5200-gpt";
0064 reg = <0x600 0x10>;
0065 interrupts = <1 9 0>;
0066 fsl,has-wdt;
0067 };
0068
0069 can@900 {
0070 compatible = "fsl,mpc5200-mscan";
0071 interrupts = <2 17 0>;
0072 reg = <0x900 0x80>;
0073 };
0074
0075 can@980 {
0076 compatible = "fsl,mpc5200-mscan";
0077 interrupts = <2 18 0>;
0078 reg = <0x980 0x80>;
0079 };
0080
0081 gpio_simple: gpio@b00 {
0082 compatible = "fsl,mpc5200-gpio";
0083 reg = <0xb00 0x40>;
0084 interrupts = <1 7 0>;
0085 gpio-controller;
0086 #gpio-cells = <2>;
0087 };
0088
0089 usb@1000 {
0090 compatible = "fsl,mpc5200-ohci","ohci-be";
0091 reg = <0x1000 0xff>;
0092 interrupts = <2 6 0>;
0093 };
0094
0095 dma-controller@1200 {
0096 compatible = "fsl,mpc5200-bestcomm";
0097 reg = <0x1200 0x80>;
0098 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
0099 3 4 0 3 5 0 3 6 0 3 7 0
0100 3 8 0 3 9 0 3 10 0 3 11 0
0101 3 12 0 3 13 0 3 14 0 3 15 0>;
0102 };
0103
0104 xlb@1f00 {
0105 compatible = "fsl,mpc5200-xlb";
0106 reg = <0x1f00 0x100>;
0107 };
0108
0109 serial@2000 { // PSC1
0110 compatible = "fsl,mpc5200-psc-uart";
0111 reg = <0x2000 0x100>;
0112 interrupts = <2 1 0>;
0113 };
0114
0115 serial@2200 { // PSC2
0116 compatible = "fsl,mpc5200-psc-uart";
0117 reg = <0x2200 0x100>;
0118 interrupts = <2 2 0>;
0119 };
0120
0121 serial@2400 { // PSC3
0122 compatible = "fsl,mpc5200-psc-uart";
0123 reg = <0x2400 0x100>;
0124 interrupts = <2 3 0>;
0125 };
0126
0127 ethernet@3000 {
0128 compatible = "fsl,mpc5200-fec";
0129 reg = <0x3000 0x400>;
0130 local-mac-address = [ 00 00 00 00 00 00 ];
0131 interrupts = <2 5 0>;
0132 phy-handle = <&phy0>;
0133 };
0134
0135 mdio@3000 {
0136 #address-cells = <1>;
0137 #size-cells = <0>;
0138 compatible = "fsl,mpc5200-mdio";
0139 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
0140 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
0141
0142 phy0: ethernet-phy@0 {
0143 reg = <0>;
0144 };
0145 };
0146
0147 ata@3a00 {
0148 compatible = "fsl,mpc5200-ata";
0149 reg = <0x3a00 0x100>;
0150 interrupts = <2 7 0>;
0151 };
0152
0153 i2c@3d40 {
0154 #address-cells = <1>;
0155 #size-cells = <0>;
0156 compatible = "fsl,mpc5200-i2c","fsl-i2c";
0157 reg = <0x3d40 0x40>;
0158 interrupts = <2 16 0>;
0159
0160 rtc@68 {
0161 compatible = "dallas,ds1307";
0162 reg = <0x68>;
0163 };
0164 };
0165
0166 sram@8000 {
0167 compatible = "fsl,mpc5200-sram";
0168 reg = <0x8000 0x4000>;
0169 };
0170 };
0171
0172 localbus {
0173 compatible = "fsl,mpc5200-lpb","simple-bus";
0174 #address-cells = <2>;
0175 #size-cells = <1>;
0176 ranges = <0 0 0xfc000000 0x02000000>;
0177
0178 flash@0,0 {
0179 compatible = "cfi-flash";
0180 reg = <0 0 0x02000000>;
0181 bank-width = <4>;
0182 device-width = <2>;
0183 #size-cells = <1>;
0184 #address-cells = <1>;
0185 };
0186 };
0187
0188 pci@f0000d00 {
0189 #interrupt-cells = <1>;
0190 #size-cells = <2>;
0191 #address-cells = <3>;
0192 device_type = "pci";
0193 compatible = "fsl,mpc5200-pci";
0194 reg = <0xf0000d00 0x100>;
0195 interrupt-map-mask = <0xf800 0 0 7>;
0196 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
0197 0xc000 0 0 2 &mpc5200_pic 0 0 3
0198 0xc000 0 0 3 &mpc5200_pic 0 0 3
0199 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
0200 clock-frequency = <0>; // From boot loader
0201 interrupts = <2 8 0 2 9 0 2 10 0>;
0202 bus-range = <0 0>;
0203 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000>,
0204 <0x02000000 0 0x90000000 0x90000000 0 0x10000000>,
0205 <0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
0206 };
0207 };
