0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * PS3 Game Console device tree.
0004 *
0005 * Copyright (C) 2007 Sony Computer Entertainment Inc.
0006 * Copyright 2007 Sony Corp.
0007 */
0008
0009 /dts-v1/;
0010
0011 / {
0012 model = "SonyPS3";
0013 compatible = "sony,ps3";
0014 #size-cells = <2>;
0015 #address-cells = <2>;
0016
0017 chosen {
0018 };
0019
0020 /*
0021 * We'll get the size of the bootmem block from lv1 after startup,
0022 * so we'll put a null entry here.
0023 */
0024
0025 memory {
0026 device_type = "memory";
0027 reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
0028 };
0029
0030 /*
0031 * The boot cpu is always zero for PS3.
0032 *
0033 * dtc expects a clock-frequency and timebase-frequency entries, so
0034 * we'll put a null entries here. These will be initialized after
0035 * startup with data from lv1.
0036 *
0037 * Seems the only way currently to indicate a processor has multiple
0038 * threads is with an ibm,ppc-interrupt-server#s entry. We'll put one
0039 * here so we can bring up both of ours. See smp_setup_cpu_maps().
0040 */
0041
0042 cpus {
0043 #size-cells = <0>;
0044 #address-cells = <1>;
0045
0046 cpu@0 {
0047 device_type = "cpu";
0048 reg = <0x00000000>;
0049 ibm,ppc-interrupt-server#s = <0x0 0x1>;
0050 clock-frequency = <0>;
0051 timebase-frequency = <0>;
0052 i-cache-size = <32768>;
0053 d-cache-size = <32768>;
0054 i-cache-line-size = <128>;
0055 d-cache-line-size = <128>;
0056 };
0057 };
0058 };
