0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source
0004 *
0005 * Copyright (C) 2006-2009 Pengutronix
0006 * Sascha Hauer, Juergen Beisert, Wolfram Sang <kernel@pengutronix.de>
0007 */
0008
0009 /include/ "mpc5200b.dtsi"
0010
0011 &gpt0 { fsl,has-wdt; };
0012 &gpt2 { gpio-controller; };
0013 &gpt3 { gpio-controller; };
0014 &gpt4 { gpio-controller; };
0015 &gpt5 { gpio-controller; };
0016 &gpt6 { gpio-controller; };
0017 &gpt7 { gpio-controller; };
0018
0019 / {
0020 model = "phytec,pcm032";
0021 compatible = "phytec,pcm032";
0022
0023 memory@0 {
0024 reg = <0x00000000 0x08000000>; // 128MB
0025 };
0026
0027 soc5200@f0000000 {
0028 psc@2000 { /* PSC1 is ac97 */
0029 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
0030 cell-index = <0>;
0031 };
0032
0033 /* PSC2 port is used by CAN1/2 */
0034 psc@2200 {
0035 status = "disabled";
0036 };
0037
0038 psc@2400 { /* PSC3 in UART mode */
0039 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
0040 };
0041
0042 /* PSC4 is ??? */
0043 psc@2600 {
0044 status = "disabled";
0045 };
0046
0047 /* PSC5 is ??? */
0048 psc@2800 {
0049 status = "disabled";
0050 };
0051
0052 psc@2c00 { /* PSC6 in UART mode */
0053 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
0054 };
0055
0056 ethernet@3000 {
0057 phy-handle = <&phy0>;
0058 };
0059
0060 mdio@3000 {
0061 phy0: ethernet-phy@0 {
0062 reg = <0>;
0063 };
0064 };
0065
0066 i2c@3d40 {
0067 rtc@51 {
0068 compatible = "nxp,pcf8563";
0069 reg = <0x51>;
0070 };
0071 eeprom@52 {
0072 compatible = "catalyst,24c32", "atmel,24c32";
0073 reg = <0x52>;
0074 pagesize = <32>;
0075 };
0076 };
0077 };
0078
0079 pci@f0000d00 {
0080 interrupt-map-mask = <0xf800 0 0 7>;
0081 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
0082 0xc000 0 0 2 &mpc5200_pic 1 1 3
0083 0xc000 0 0 3 &mpc5200_pic 1 2 3
0084 0xc000 0 0 4 &mpc5200_pic 1 3 3
0085
0086 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
0087 0xc800 0 0 2 &mpc5200_pic 1 2 3
0088 0xc800 0 0 3 &mpc5200_pic 1 3 3
0089 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
0090 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000>,
0091 <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000>,
0092 <0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
0093 };
0094
0095 localbus {
0096 ranges = <0 0 0xfe000000 0x02000000
0097 1 0 0xfc000000 0x02000000
0098 2 0 0xfbe00000 0x00200000
0099 3 0 0xf9e00000 0x02000000
0100 4 0 0xf7e00000 0x02000000
0101 5 0 0xe6000000 0x02000000
0102 6 0 0xe8000000 0x02000000
0103 7 0 0xea000000 0x02000000>;
0104
0105 flash@0,0 {
0106 compatible = "cfi-flash";
0107 reg = <0 0 0x02000000>;
0108 bank-width = <4>;
0109 #size-cells = <1>;
0110 #address-cells = <1>;
0111
0112 partition@0 {
0113 label = "ubootl";
0114 reg = <0x00000000 0x00040000>;
0115 };
0116 partition@40000 {
0117 label = "kernel";
0118 reg = <0x00040000 0x001c0000>;
0119 };
0120 partition@200000 {
0121 label = "jffs2";
0122 reg = <0x00200000 0x01d00000>;
0123 };
0124 partition@1f00000 {
0125 label = "uboot";
0126 reg = <0x01f00000 0x00040000>;
0127 };
0128 partition@1f40000 {
0129 label = "env";
0130 reg = <0x01f40000 0x00040000>;
0131 };
0132 partition@1f80000 {
0133 label = "oftree";
0134 reg = <0x01f80000 0x00040000>;
0135 };
0136 partition@1fc0000 {
0137 label = "space";
0138 reg = <0x01fc0000 0x00040000>;
0139 };
0140 };
0141
0142 sram@2,0 {
0143 compatible = "mtd-ram";
0144 reg = <2 0 0x00200000>;
0145 bank-width = <2>;
0146 };
0147
0148 /*
0149 * example snippets for FPGA
0150 *
0151 * fpga@3,0 {
0152 * compatible = "fpga_driver";
0153 * reg = <3 0 0x02000000>;
0154 * bank-width = <4>;
0155 * };
0156 *
0157 * fpga@4,0 {
0158 * compatible = "fpga_driver";
0159 * reg = <4 0 0x02000000>;
0160 * bank-width = <4>;
0161 * };
0162 */
0163
0164 /*
0165 * example snippets for free chipselects
0166 *
0167 * device@5,0 {
0168 * compatible = "custom_driver";
0169 * reg = <5 0 0x02000000>;
0170 * };
0171 *
0172 * device@6,0 {
0173 * compatible = "custom_driver";
0174 * reg = <6 0 0x02000000>;
0175 * };
0176 *
0177 * device@7,0 {
0178 * compatible = "custom_driver";
0179 * reg = <7 0 0x02000000>;
0180 * };
0181 */
0182 };
0183 };
