0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * MPC8610 HPCD Device Tree Source
0004 *
0005 * Copyright 2007-2008 Freescale Semiconductor Inc.
0006 */
0007
0008 /dts-v1/;
0009
0010 / {
0011 model = "MPC8610HPCD";
0012 compatible = "fsl,MPC8610HPCD";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 aliases {
0017 serial0 = &serial0;
0018 serial1 = &serial1;
0019 pci0 = &pci0;
0020 pci1 = &pci1;
0021 pci2 = &pci2;
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 PowerPC,8610@0 {
0029 device_type = "cpu";
0030 reg = <0>;
0031 d-cache-line-size = <32>;
0032 i-cache-line-size = <32>;
0033 d-cache-size = <32768>; // L1
0034 i-cache-size = <32768>; // L1
0035 sleep = <&pmc 0x00008000 0 // core
0036 &pmc 0x00004000 0>; // timebase
0037 timebase-frequency = <0>; // From uboot
0038 bus-frequency = <0>; // From uboot
0039 clock-frequency = <0>; // From uboot
0040 };
0041 };
0042
0043 memory {
0044 device_type = "memory";
0045 reg = <0x00000000 0x20000000>; // 512M at 0x0
0046 };
0047
0048 localbus@e0005000 {
0049 #address-cells = <2>;
0050 #size-cells = <1>;
0051 compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
0052 reg = <0xe0005000 0x1000>;
0053 interrupts = <19 2>;
0054 interrupt-parent = <&mpic>;
0055 ranges = <0 0 0xf8000000 0x08000000
0056 1 0 0xf0000000 0x08000000
0057 2 0 0xe8400000 0x00008000
0058 4 0 0xe8440000 0x00008000
0059 5 0 0xe8480000 0x00008000
0060 6 0 0xe84c0000 0x00008000
0061 3 0 0xe8000000 0x00000020>;
0062 sleep = <&pmc 0x08000000 0>;
0063
0064 flash@0,0 {
0065 compatible = "cfi-flash";
0066 reg = <0 0 0x8000000>;
0067 bank-width = <2>;
0068 device-width = <1>;
0069 };
0070
0071 flash@1,0 {
0072 compatible = "cfi-flash";
0073 reg = <1 0 0x8000000>;
0074 bank-width = <2>;
0075 device-width = <1>;
0076 };
0077
0078 flash@2,0 {
0079 compatible = "fsl,mpc8610-fcm-nand",
0080 "fsl,elbc-fcm-nand";
0081 reg = <2 0 0x8000>;
0082 };
0083
0084 flash@4,0 {
0085 compatible = "fsl,mpc8610-fcm-nand",
0086 "fsl,elbc-fcm-nand";
0087 reg = <4 0 0x8000>;
0088 };
0089
0090 flash@5,0 {
0091 compatible = "fsl,mpc8610-fcm-nand",
0092 "fsl,elbc-fcm-nand";
0093 reg = <5 0 0x8000>;
0094 };
0095
0096 flash@6,0 {
0097 compatible = "fsl,mpc8610-fcm-nand",
0098 "fsl,elbc-fcm-nand";
0099 reg = <6 0 0x8000>;
0100 };
0101
0102 board-control@3,0 {
0103 #address-cells = <1>;
0104 #size-cells = <1>;
0105 compatible = "fsl,fpga-pixis";
0106 reg = <3 0 0x20>;
0107 ranges = <0 3 0 0x20>;
0108 interrupt-parent = <&mpic>;
0109 interrupts = <8 8>;
0110
0111 sdcsr_pio: gpio-controller@a {
0112 #gpio-cells = <2>;
0113 compatible = "fsl,fpga-pixis-gpio-bank";
0114 reg = <0xa 1>;
0115 gpio-controller;
0116 };
0117 };
0118 };
0119
0120 soc@e0000000 {
0121 #address-cells = <1>;
0122 #size-cells = <1>;
0123 #interrupt-cells = <2>;
0124 device_type = "soc";
0125 compatible = "fsl,mpc8610-immr", "simple-bus";
0126 ranges = <0x0 0xe0000000 0x00100000>;
0127 bus-frequency = <0>;
0128
0129 mcm-law@0 {
0130 compatible = "fsl,mcm-law";
0131 reg = <0x0 0x1000>;
0132 fsl,num-laws = <10>;
0133 };
0134
0135 mcm@1000 {
0136 compatible = "fsl,mpc8610-mcm", "fsl,mcm";
0137 reg = <0x1000 0x1000>;
0138 interrupts = <17 2>;
0139 interrupt-parent = <&mpic>;
0140 };
0141
0142 i2c@3000 {
0143 #address-cells = <1>;
0144 #size-cells = <0>;
0145 cell-index = <0>;
0146 compatible = "fsl-i2c";
0147 reg = <0x3000 0x100>;
0148 interrupts = <43 2>;
0149 interrupt-parent = <&mpic>;
0150 dfsrr;
0151
0152 cs4270:codec@4f {
0153 compatible = "cirrus,cs4270";
0154 reg = <0x4f>;
0155 /* MCLK source is a stand-alone oscillator */
0156 clock-frequency = <12288000>;
0157 };
0158 };
0159
0160 i2c@3100 {
0161 #address-cells = <1>;
0162 #size-cells = <0>;
0163 cell-index = <1>;
0164 compatible = "fsl-i2c";
0165 reg = <0x3100 0x100>;
0166 interrupts = <43 2>;
0167 interrupt-parent = <&mpic>;
0168 sleep = <&pmc 0x00000004 0>;
0169 dfsrr;
0170 };
0171
0172 serial0: serial@4500 {
0173 cell-index = <0>;
0174 device_type = "serial";
0175 compatible = "fsl,ns16550", "ns16550";
0176 reg = <0x4500 0x100>;
0177 clock-frequency = <0>;
0178 interrupts = <42 2>;
0179 interrupt-parent = <&mpic>;
0180 sleep = <&pmc 0x00000002 0>;
0181 };
0182
0183 serial1: serial@4600 {
0184 cell-index = <1>;
0185 device_type = "serial";
0186 compatible = "fsl,ns16550", "ns16550";
0187 reg = <0x4600 0x100>;
0188 clock-frequency = <0>;
0189 interrupts = <42 2>;
0190 interrupt-parent = <&mpic>;
0191 sleep = <&pmc 0x00000008 0>;
0192 };
0193
0194 spi@7000 {
0195 #address-cells = <1>;
0196 #size-cells = <0>;
0197 compatible = "fsl,mpc8610-spi", "fsl,spi";
0198 reg = <0x7000 0x40>;
0199 cell-index = <0>;
0200 interrupts = <59 2>;
0201 interrupt-parent = <&mpic>;
0202 mode = "cpu";
0203 cs-gpios = <&sdcsr_pio 7 0>;
0204 sleep = <&pmc 0x00000800 0>;
0205
0206 mmc-slot@0 {
0207 compatible = "fsl,mpc8610hpcd-mmc-slot",
0208 "mmc-spi-slot";
0209 reg = <0>;
0210 gpios = <&sdcsr_pio 0 1 /* nCD */
0211 &sdcsr_pio 1 0>; /* WP */
0212 voltage-ranges = <3300 3300>;
0213 spi-max-frequency = <50000000>;
0214 };
0215 };
0216
0217 display@2c000 {
0218 compatible = "fsl,diu";
0219 reg = <0x2c000 100>;
0220 interrupts = <72 2>;
0221 interrupt-parent = <&mpic>;
0222 sleep = <&pmc 0x04000000 0>;
0223 };
0224
0225 mpic: interrupt-controller@40000 {
0226 interrupt-controller;
0227 #address-cells = <0>;
0228 #interrupt-cells = <2>;
0229 reg = <0x40000 0x40000>;
0230 compatible = "chrp,open-pic";
0231 device_type = "open-pic";
0232 };
0233
0234 msi@41600 {
0235 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
0236 reg = <0x41600 0x80>;
0237 msi-available-ranges = <0 0x100>;
0238 interrupts = <
0239 0xe0 0
0240 0xe1 0
0241 0xe2 0
0242 0xe3 0
0243 0xe4 0
0244 0xe5 0
0245 0xe6 0
0246 0xe7 0>;
0247 interrupt-parent = <&mpic>;
0248 };
0249
0250 global-utilities@e0000 {
0251 #address-cells = <1>;
0252 #size-cells = <1>;
0253 compatible = "fsl,mpc8610-guts";
0254 reg = <0xe0000 0x1000>;
0255 ranges = <0 0xe0000 0x1000>;
0256 fsl,has-rstcr;
0257
0258 pmc: power@70 {
0259 compatible = "fsl,mpc8610-pmc",
0260 "fsl,mpc8641d-pmc";
0261 reg = <0x70 0x20>;
0262 };
0263 };
0264
0265 wdt@e4000 {
0266 compatible = "fsl,mpc8610-wdt";
0267 reg = <0xe4000 0x100>;
0268 };
0269
0270 ssi@16000 {
0271 compatible = "fsl,mpc8610-ssi";
0272 cell-index = <0>;
0273 reg = <0x16000 0x100>;
0274 interrupt-parent = <&mpic>;
0275 interrupts = <62 2>;
0276 fsl,mode = "i2s-slave";
0277 codec-handle = <&cs4270>;
0278 fsl,playback-dma = <&dma00>;
0279 fsl,capture-dma = <&dma01>;
0280 fsl,fifo-depth = <8>;
0281 sleep = <&pmc 0 0x08000000>;
0282 };
0283
0284 ssi@16100 {
0285 compatible = "fsl,mpc8610-ssi";
0286 status = "disabled";
0287 cell-index = <1>;
0288 reg = <0x16100 0x100>;
0289 interrupt-parent = <&mpic>;
0290 interrupts = <63 2>;
0291 fsl,fifo-depth = <8>;
0292 sleep = <&pmc 0 0x04000000>;
0293 };
0294
0295 dma@21300 {
0296 #address-cells = <1>;
0297 #size-cells = <1>;
0298 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
0299 cell-index = <0>;
0300 reg = <0x21300 0x4>; /* DMA general status register */
0301 ranges = <0x0 0x21100 0x200>;
0302 sleep = <&pmc 0x00000400 0>;
0303
0304 dma00: dma-channel@0 {
0305 compatible = "fsl,mpc8610-dma-channel",
0306 "fsl,ssi-dma-channel";
0307 cell-index = <0>;
0308 reg = <0x0 0x80>;
0309 interrupt-parent = <&mpic>;
0310 interrupts = <20 2>;
0311 };
0312 dma01: dma-channel@1 {
0313 compatible = "fsl,mpc8610-dma-channel",
0314 "fsl,ssi-dma-channel";
0315 cell-index = <1>;
0316 reg = <0x80 0x80>;
0317 interrupt-parent = <&mpic>;
0318 interrupts = <21 2>;
0319 };
0320 dma-channel@2 {
0321 compatible = "fsl,mpc8610-dma-channel",
0322 "fsl,eloplus-dma-channel";
0323 cell-index = <2>;
0324 reg = <0x100 0x80>;
0325 interrupt-parent = <&mpic>;
0326 interrupts = <22 2>;
0327 };
0328 dma-channel@3 {
0329 compatible = "fsl,mpc8610-dma-channel",
0330 "fsl,eloplus-dma-channel";
0331 cell-index = <3>;
0332 reg = <0x180 0x80>;
0333 interrupt-parent = <&mpic>;
0334 interrupts = <23 2>;
0335 };
0336 };
0337
0338 dma@c300 {
0339 #address-cells = <1>;
0340 #size-cells = <1>;
0341 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
0342 cell-index = <1>;
0343 reg = <0xc300 0x4>; /* DMA general status register */
0344 ranges = <0x0 0xc100 0x200>;
0345 sleep = <&pmc 0x00000200 0>;
0346
0347 dma-channel@0 {
0348 compatible = "fsl,mpc8610-dma-channel",
0349 "fsl,eloplus-dma-channel";
0350 cell-index = <0>;
0351 reg = <0x0 0x80>;
0352 interrupt-parent = <&mpic>;
0353 interrupts = <76 2>;
0354 };
0355 dma-channel@1 {
0356 compatible = "fsl,mpc8610-dma-channel",
0357 "fsl,eloplus-dma-channel";
0358 cell-index = <1>;
0359 reg = <0x80 0x80>;
0360 interrupt-parent = <&mpic>;
0361 interrupts = <77 2>;
0362 };
0363 dma-channel@2 {
0364 compatible = "fsl,mpc8610-dma-channel",
0365 "fsl,eloplus-dma-channel";
0366 cell-index = <2>;
0367 reg = <0x100 0x80>;
0368 interrupt-parent = <&mpic>;
0369 interrupts = <78 2>;
0370 };
0371 dma-channel@3 {
0372 compatible = "fsl,mpc8610-dma-channel",
0373 "fsl,eloplus-dma-channel";
0374 cell-index = <3>;
0375 reg = <0x180 0x80>;
0376 interrupt-parent = <&mpic>;
0377 interrupts = <79 2>;
0378 };
0379 };
0380
0381 };
0382
0383 pci0: pci@e0008000 {
0384 compatible = "fsl,mpc8610-pci";
0385 device_type = "pci";
0386 #interrupt-cells = <1>;
0387 #size-cells = <2>;
0388 #address-cells = <3>;
0389 reg = <0xe0008000 0x1000>;
0390 bus-range = <0 0>;
0391 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0392 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
0393 sleep = <&pmc 0x80000000 0>;
0394 clock-frequency = <33333333>;
0395 interrupt-parent = <&mpic>;
0396 interrupts = <24 2>;
0397 interrupt-map-mask = <0xf800 0 0 7>;
0398 interrupt-map = <
0399 /* IDSEL 0x11 */
0400 0x8800 0 0 1 &mpic 4 1
0401 0x8800 0 0 2 &mpic 5 1
0402 0x8800 0 0 3 &mpic 6 1
0403 0x8800 0 0 4 &mpic 7 1
0404
0405 /* IDSEL 0x12 */
0406 0x9000 0 0 1 &mpic 5 1
0407 0x9000 0 0 2 &mpic 6 1
0408 0x9000 0 0 3 &mpic 7 1
0409 0x9000 0 0 4 &mpic 4 1
0410 >;
0411 };
0412
0413 pci1: pcie@e000a000 {
0414 compatible = "fsl,mpc8641-pcie";
0415 device_type = "pci";
0416 #interrupt-cells = <1>;
0417 #size-cells = <2>;
0418 #address-cells = <3>;
0419 reg = <0xe000a000 0x1000>;
0420 bus-range = <1 3>;
0421 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0422 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
0423 sleep = <&pmc 0x40000000 0>;
0424 clock-frequency = <33333333>;
0425 interrupt-parent = <&mpic>;
0426 interrupts = <26 2>;
0427 interrupt-map-mask = <0xf800 0 0 7>;
0428
0429 interrupt-map = <
0430 /* IDSEL 0x1b */
0431 0xd800 0 0 1 &mpic 2 1
0432
0433 /* IDSEL 0x1c*/
0434 0xe000 0 0 1 &mpic 1 1
0435 0xe000 0 0 2 &mpic 1 1
0436 0xe000 0 0 3 &mpic 1 1
0437 0xe000 0 0 4 &mpic 1 1
0438
0439 /* IDSEL 0x1f */
0440 0xf800 0 0 1 &mpic 3 2
0441 0xf800 0 0 2 &mpic 0 1
0442 >;
0443
0444 pcie@0 {
0445 reg = <0 0 0 0 0>;
0446 #size-cells = <2>;
0447 #address-cells = <3>;
0448 device_type = "pci";
0449 ranges = <0x02000000 0x0 0xa0000000
0450 0x02000000 0x0 0xa0000000
0451 0x0 0x10000000
0452 0x01000000 0x0 0x00000000
0453 0x01000000 0x0 0x00000000
0454 0x0 0x00100000>;
0455 uli1575@0 {
0456 reg = <0 0 0 0 0>;
0457 #size-cells = <2>;
0458 #address-cells = <3>;
0459 ranges = <0x02000000 0x0 0xa0000000
0460 0x02000000 0x0 0xa0000000
0461 0x0 0x10000000
0462 0x01000000 0x0 0x00000000
0463 0x01000000 0x0 0x00000000
0464 0x0 0x00100000>;
0465
0466 isa@1e {
0467 device_type = "isa";
0468 #size-cells = <1>;
0469 #address-cells = <2>;
0470 reg = <0xf000 0 0 0 0>;
0471 ranges = <1 0 0x01000000 0 0
0472 0x00001000>;
0473
0474 rtc@70 {
0475 compatible = "pnpPNP,b00";
0476 reg = <1 0x70 2>;
0477 };
0478 };
0479 };
0480 };
0481 };
0482
0483 pci2: pcie@e0009000 {
0484 #address-cells = <3>;
0485 #size-cells = <2>;
0486 #interrupt-cells = <1>;
0487 device_type = "pci";
0488 compatible = "fsl,mpc8641-pcie";
0489 reg = <0xe0009000 0x00001000>;
0490 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
0491 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
0492 bus-range = <0 255>;
0493 interrupt-map-mask = <0xf800 0 0 7>;
0494 interrupt-map = <0x0000 0 0 1 &mpic 4 1
0495 0x0000 0 0 2 &mpic 5 1
0496 0x0000 0 0 3 &mpic 6 1
0497 0x0000 0 0 4 &mpic 7 1>;
0498 interrupt-parent = <&mpic>;
0499 interrupts = <25 2>;
0500 sleep = <&pmc 0x20000000 0>;
0501 clock-frequency = <33333333>;
0502 };
0503 };
