0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8378E MDS Device Tree Source
0004 *
0005 * Copyright 2007 Freescale Semiconductor Inc.
0006 */
0007
0008 /dts-v1/;
0009
0010 / {
0011 model = "fsl,mpc8378emds";
0012 compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 aliases {
0017 ethernet0 = &enet0;
0018 ethernet1 = &enet1;
0019 serial0 = &serial0;
0020 serial1 = &serial1;
0021 pci0 = &pci0;
0022 pci1 = &pci1;
0023 pci2 = &pci2;
0024 };
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029
0030 PowerPC,8378@0 {
0031 device_type = "cpu";
0032 reg = <0x0>;
0033 d-cache-line-size = <32>;
0034 i-cache-line-size = <32>;
0035 d-cache-size = <32768>;
0036 i-cache-size = <32768>;
0037 timebase-frequency = <0>;
0038 bus-frequency = <0>;
0039 clock-frequency = <0>;
0040 };
0041 };
0042
0043 memory {
0044 device_type = "memory";
0045 reg = <0x00000000 0x20000000>; // 512MB at 0
0046 };
0047
0048 localbus@e0005000 {
0049 #address-cells = <2>;
0050 #size-cells = <1>;
0051 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
0052 reg = <0xe0005000 0x1000>;
0053 interrupts = <77 0x8>;
0054 interrupt-parent = <&ipic>;
0055
0056 // booting from NOR flash
0057 ranges = <0 0x0 0xfe000000 0x02000000
0058 1 0x0 0xf8000000 0x00008000
0059 3 0x0 0xe0600000 0x00008000>;
0060
0061 flash@0,0 {
0062 #address-cells = <1>;
0063 #size-cells = <1>;
0064 compatible = "cfi-flash";
0065 reg = <0 0x0 0x2000000>;
0066 bank-width = <2>;
0067 device-width = <1>;
0068
0069 u-boot@0 {
0070 reg = <0x0 0x100000>;
0071 read-only;
0072 };
0073
0074 fs@100000 {
0075 reg = <0x100000 0x800000>;
0076 };
0077
0078 kernel@1d00000 {
0079 reg = <0x1d00000 0x200000>;
0080 };
0081
0082 dtb@1f00000 {
0083 reg = <0x1f00000 0x100000>;
0084 };
0085 };
0086
0087 bcsr@1,0 {
0088 reg = <1 0x0 0x8000>;
0089 compatible = "fsl,mpc837xmds-bcsr";
0090 };
0091
0092 nand@3,0 {
0093 #address-cells = <1>;
0094 #size-cells = <1>;
0095 compatible = "fsl,mpc8378-fcm-nand",
0096 "fsl,elbc-fcm-nand";
0097 reg = <3 0x0 0x8000>;
0098
0099 u-boot@0 {
0100 reg = <0x0 0x100000>;
0101 read-only;
0102 };
0103
0104 kernel@100000 {
0105 reg = <0x100000 0x300000>;
0106 };
0107
0108 fs@400000 {
0109 reg = <0x400000 0x1c00000>;
0110 };
0111 };
0112 };
0113
0114 soc@e0000000 {
0115 #address-cells = <1>;
0116 #size-cells = <1>;
0117 device_type = "soc";
0118 compatible = "simple-bus";
0119 ranges = <0x0 0xe0000000 0x00100000>;
0120 reg = <0xe0000000 0x00000200>;
0121 bus-frequency = <0>;
0122
0123 wdt@200 {
0124 compatible = "mpc83xx_wdt";
0125 reg = <0x200 0x100>;
0126 };
0127
0128 sleep-nexus {
0129 #address-cells = <1>;
0130 #size-cells = <1>;
0131 compatible = "simple-bus";
0132 sleep = <&pmc 0x0c000000>;
0133 ranges;
0134
0135 i2c@3000 {
0136 #address-cells = <1>;
0137 #size-cells = <0>;
0138 cell-index = <0>;
0139 compatible = "fsl-i2c";
0140 reg = <0x3000 0x100>;
0141 interrupts = <14 0x8>;
0142 interrupt-parent = <&ipic>;
0143 dfsrr;
0144
0145 rtc@68 {
0146 compatible = "dallas,ds1374";
0147 reg = <0x68>;
0148 interrupts = <19 0x8>;
0149 interrupt-parent = <&ipic>;
0150 };
0151 };
0152
0153 sdhci@2e000 {
0154 compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
0155 reg = <0x2e000 0x1000>;
0156 interrupts = <42 0x8>;
0157 interrupt-parent = <&ipic>;
0158 sdhci,wp-inverted;
0159 /* Filled in by U-Boot */
0160 clock-frequency = <0>;
0161 };
0162 };
0163
0164 i2c@3100 {
0165 #address-cells = <1>;
0166 #size-cells = <0>;
0167 cell-index = <1>;
0168 compatible = "fsl-i2c";
0169 reg = <0x3100 0x100>;
0170 interrupts = <15 0x8>;
0171 interrupt-parent = <&ipic>;
0172 dfsrr;
0173 };
0174
0175 spi@7000 {
0176 cell-index = <0>;
0177 compatible = "fsl,spi";
0178 reg = <0x7000 0x1000>;
0179 interrupts = <16 0x8>;
0180 interrupt-parent = <&ipic>;
0181 mode = "cpu";
0182 };
0183
0184 dma@82a8 {
0185 #address-cells = <1>;
0186 #size-cells = <1>;
0187 compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
0188 reg = <0x82a8 4>;
0189 ranges = <0 0x8100 0x1a8>;
0190 interrupt-parent = <&ipic>;
0191 interrupts = <71 8>;
0192 cell-index = <0>;
0193 dma-channel@0 {
0194 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
0195 reg = <0 0x80>;
0196 cell-index = <0>;
0197 interrupt-parent = <&ipic>;
0198 interrupts = <71 8>;
0199 };
0200 dma-channel@80 {
0201 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
0202 reg = <0x80 0x80>;
0203 cell-index = <1>;
0204 interrupt-parent = <&ipic>;
0205 interrupts = <71 8>;
0206 };
0207 dma-channel@100 {
0208 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
0209 reg = <0x100 0x80>;
0210 cell-index = <2>;
0211 interrupt-parent = <&ipic>;
0212 interrupts = <71 8>;
0213 };
0214 dma-channel@180 {
0215 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
0216 reg = <0x180 0x28>;
0217 cell-index = <3>;
0218 interrupt-parent = <&ipic>;
0219 interrupts = <71 8>;
0220 };
0221 };
0222
0223 usb@23000 {
0224 compatible = "fsl-usb2-dr";
0225 reg = <0x23000 0x1000>;
0226 #address-cells = <1>;
0227 #size-cells = <0>;
0228 interrupt-parent = <&ipic>;
0229 interrupts = <38 0x8>;
0230 dr_mode = "host";
0231 phy_type = "ulpi";
0232 sleep = <&pmc 0x00c00000>;
0233 };
0234
0235 enet0: ethernet@24000 {
0236 #address-cells = <1>;
0237 #size-cells = <1>;
0238 cell-index = <0>;
0239 device_type = "network";
0240 model = "eTSEC";
0241 compatible = "gianfar";
0242 reg = <0x24000 0x1000>;
0243 ranges = <0x0 0x24000 0x1000>;
0244 local-mac-address = [ 00 00 00 00 00 00 ];
0245 interrupts = <32 0x8 33 0x8 34 0x8>;
0246 phy-connection-type = "mii";
0247 interrupt-parent = <&ipic>;
0248 tbi-handle = <&tbi0>;
0249 phy-handle = <&phy2>;
0250 sleep = <&pmc 0xc0000000>;
0251 fsl,magic-packet;
0252
0253 mdio@520 {
0254 #address-cells = <1>;
0255 #size-cells = <0>;
0256 compatible = "fsl,gianfar-mdio";
0257 reg = <0x520 0x20>;
0258
0259 phy2: ethernet-phy@2 {
0260 interrupt-parent = <&ipic>;
0261 interrupts = <17 0x8>;
0262 reg = <0x2>;
0263 };
0264
0265 phy3: ethernet-phy@3 {
0266 interrupt-parent = <&ipic>;
0267 interrupts = <18 0x8>;
0268 reg = <0x3>;
0269 };
0270
0271 tbi0: tbi-phy@11 {
0272 reg = <0x11>;
0273 device_type = "tbi-phy";
0274 };
0275 };
0276 };
0277
0278 enet1: ethernet@25000 {
0279 #address-cells = <1>;
0280 #size-cells = <1>;
0281 cell-index = <1>;
0282 device_type = "network";
0283 model = "eTSEC";
0284 compatible = "gianfar";
0285 reg = <0x25000 0x1000>;
0286 ranges = <0x0 0x25000 0x1000>;
0287 local-mac-address = [ 00 00 00 00 00 00 ];
0288 interrupts = <35 0x8 36 0x8 37 0x8>;
0289 phy-connection-type = "mii";
0290 interrupt-parent = <&ipic>;
0291 tbi-handle = <&tbi1>;
0292 phy-handle = <&phy3>;
0293 sleep = <&pmc 0x30000000>;
0294 fsl,magic-packet;
0295
0296 mdio@520 {
0297 #address-cells = <1>;
0298 #size-cells = <0>;
0299 compatible = "fsl,gianfar-tbi";
0300 reg = <0x520 0x20>;
0301
0302 tbi1: tbi-phy@11 {
0303 reg = <0x11>;
0304 device_type = "tbi-phy";
0305 };
0306 };
0307 };
0308
0309 serial0: serial@4500 {
0310 cell-index = <0>;
0311 device_type = "serial";
0312 compatible = "fsl,ns16550", "ns16550";
0313 reg = <0x4500 0x100>;
0314 clock-frequency = <0>;
0315 interrupts = <9 0x8>;
0316 interrupt-parent = <&ipic>;
0317 };
0318
0319 serial1: serial@4600 {
0320 cell-index = <1>;
0321 device_type = "serial";
0322 compatible = "fsl,ns16550", "ns16550";
0323 reg = <0x4600 0x100>;
0324 clock-frequency = <0>;
0325 interrupts = <10 0x8>;
0326 interrupt-parent = <&ipic>;
0327 };
0328
0329 crypto@30000 {
0330 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
0331 "fsl,sec2.1", "fsl,sec2.0";
0332 reg = <0x30000 0x10000>;
0333 interrupts = <11 0x8>;
0334 interrupt-parent = <&ipic>;
0335 fsl,num-channels = <4>;
0336 fsl,channel-fifo-len = <24>;
0337 fsl,exec-units-mask = <0x9fe>;
0338 fsl,descriptor-types-mask = <0x3ab0ebf>;
0339 sleep = <&pmc 0x03000000>;
0340 };
0341
0342 /* IPIC
0343 * interrupts cell = <intr #, sense>
0344 * sense values match linux IORESOURCE_IRQ_* defines:
0345 * sense == 8: Level, low assertion
0346 * sense == 2: Edge, high-to-low change
0347 */
0348 ipic: pic@700 {
0349 compatible = "fsl,ipic";
0350 interrupt-controller;
0351 #address-cells = <0>;
0352 #interrupt-cells = <2>;
0353 reg = <0x700 0x100>;
0354 };
0355
0356 pmc: power@b00 {
0357 compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
0358 reg = <0xb00 0x100 0xa00 0x100>;
0359 interrupts = <80 0x8>;
0360 interrupt-parent = <&ipic>;
0361 };
0362 };
0363
0364 pci0: pci@e0008500 {
0365 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0366 interrupt-map = <
0367
0368 /* IDSEL 0x11 */
0369 0x8800 0x0 0x0 0x1 &ipic 20 0x8
0370 0x8800 0x0 0x0 0x2 &ipic 21 0x8
0371 0x8800 0x0 0x0 0x3 &ipic 22 0x8
0372 0x8800 0x0 0x0 0x4 &ipic 23 0x8
0373
0374 /* IDSEL 0x12 */
0375 0x9000 0x0 0x0 0x1 &ipic 22 0x8
0376 0x9000 0x0 0x0 0x2 &ipic 23 0x8
0377 0x9000 0x0 0x0 0x3 &ipic 20 0x8
0378 0x9000 0x0 0x0 0x4 &ipic 21 0x8
0379
0380 /* IDSEL 0x13 */
0381 0x9800 0x0 0x0 0x1 &ipic 23 0x8
0382 0x9800 0x0 0x0 0x2 &ipic 20 0x8
0383 0x9800 0x0 0x0 0x3 &ipic 21 0x8
0384 0x9800 0x0 0x0 0x4 &ipic 22 0x8
0385
0386 /* IDSEL 0x15 */
0387 0xa800 0x0 0x0 0x1 &ipic 20 0x8
0388 0xa800 0x0 0x0 0x2 &ipic 21 0x8
0389 0xa800 0x0 0x0 0x3 &ipic 22 0x8
0390 0xa800 0x0 0x0 0x4 &ipic 23 0x8
0391
0392 /* IDSEL 0x16 */
0393 0xb000 0x0 0x0 0x1 &ipic 23 0x8
0394 0xb000 0x0 0x0 0x2 &ipic 20 0x8
0395 0xb000 0x0 0x0 0x3 &ipic 21 0x8
0396 0xb000 0x0 0x0 0x4 &ipic 22 0x8
0397
0398 /* IDSEL 0x17 */
0399 0xb800 0x0 0x0 0x1 &ipic 22 0x8
0400 0xb800 0x0 0x0 0x2 &ipic 23 0x8
0401 0xb800 0x0 0x0 0x3 &ipic 20 0x8
0402 0xb800 0x0 0x0 0x4 &ipic 21 0x8
0403
0404 /* IDSEL 0x18 */
0405 0xc000 0x0 0x0 0x1 &ipic 21 0x8
0406 0xc000 0x0 0x0 0x2 &ipic 22 0x8
0407 0xc000 0x0 0x0 0x3 &ipic 23 0x8
0408 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
0409 interrupt-parent = <&ipic>;
0410 interrupts = <66 0x8>;
0411 bus-range = <0x0 0x0>;
0412 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0413 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0414 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
0415 clock-frequency = <0>;
0416 sleep = <&pmc 0x00010000>;
0417 #interrupt-cells = <1>;
0418 #size-cells = <2>;
0419 #address-cells = <3>;
0420 reg = <0xe0008500 0x100 /* internal registers */
0421 0xe0008300 0x8>; /* config space access registers */
0422 compatible = "fsl,mpc8349-pci";
0423 device_type = "pci";
0424 };
0425
0426 pci1: pcie@e0009000 {
0427 #address-cells = <3>;
0428 #size-cells = <2>;
0429 #interrupt-cells = <1>;
0430 device_type = "pci";
0431 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
0432 reg = <0xe0009000 0x00001000>;
0433 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
0434 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
0435 bus-range = <0 255>;
0436 interrupt-map-mask = <0xf800 0 0 7>;
0437 interrupt-map = <0 0 0 1 &ipic 1 8
0438 0 0 0 2 &ipic 1 8
0439 0 0 0 3 &ipic 1 8
0440 0 0 0 4 &ipic 1 8>;
0441 sleep = <&pmc 0x00300000>;
0442 clock-frequency = <0>;
0443
0444 pcie@0 {
0445 #address-cells = <3>;
0446 #size-cells = <2>;
0447 device_type = "pci";
0448 reg = <0 0 0 0 0>;
0449 ranges = <0x02000000 0 0xa8000000
0450 0x02000000 0 0xa8000000
0451 0 0x10000000
0452 0x01000000 0 0x00000000
0453 0x01000000 0 0x00000000
0454 0 0x00800000>;
0455 };
0456 };
0457
0458 pci2: pcie@e000a000 {
0459 #address-cells = <3>;
0460 #size-cells = <2>;
0461 #interrupt-cells = <1>;
0462 device_type = "pci";
0463 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
0464 reg = <0xe000a000 0x00001000>;
0465 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
0466 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
0467 bus-range = <0 255>;
0468 interrupt-map-mask = <0xf800 0 0 7>;
0469 interrupt-map = <0 0 0 1 &ipic 2 8
0470 0 0 0 2 &ipic 2 8
0471 0 0 0 3 &ipic 2 8
0472 0 0 0 4 &ipic 2 8>;
0473 sleep = <&pmc 0x000c0000>;
0474 clock-frequency = <0>;
0475
0476 pcie@0 {
0477 #address-cells = <3>;
0478 #size-cells = <2>;
0479 device_type = "pci";
0480 reg = <0 0 0 0 0>;
0481 ranges = <0x02000000 0 0xc8000000
0482 0x02000000 0 0xc8000000
0483 0 0x10000000
0484 0x01000000 0 0x00000000
0485 0x01000000 0 0x00000000
0486 0 0x00800000>;
0487 };
0488 };
0489 };
