0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8360E RDK Device Tree Source
0004 *
0005 * Copyright 2006 Freescale Semiconductor Inc.
0006 * Copyright 2007-2008 MontaVista Software, Inc.
0007 *
0008 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
0009 */
0010
0011 /dts-v1/;
0012
0013 / {
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016 compatible = "fsl,mpc8360rdk";
0017
0018 aliases {
0019 serial0 = &serial0;
0020 serial1 = &serial1;
0021 serial2 = &serial2;
0022 serial3 = &serial3;
0023 ethernet0 = &enet0;
0024 ethernet1 = &enet1;
0025 ethernet2 = &enet2;
0026 ethernet3 = &enet3;
0027 pci0 = &pci0;
0028 };
0029
0030 cpus {
0031 #address-cells = <1>;
0032 #size-cells = <0>;
0033
0034 PowerPC,8360@0 {
0035 device_type = "cpu";
0036 reg = <0>;
0037 d-cache-line-size = <32>;
0038 i-cache-line-size = <32>;
0039 d-cache-size = <32768>;
0040 i-cache-size = <32768>;
0041 /* filled by u-boot */
0042 timebase-frequency = <0>;
0043 bus-frequency = <0>;
0044 clock-frequency = <0>;
0045 };
0046 };
0047
0048 memory {
0049 device_type = "memory";
0050 /* filled by u-boot */
0051 reg = <0 0>;
0052 };
0053
0054 soc@e0000000 {
0055 #address-cells = <1>;
0056 #size-cells = <1>;
0057 device_type = "soc";
0058 compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc",
0059 "simple-bus";
0060 ranges = <0 0xe0000000 0x200000>;
0061 reg = <0xe0000000 0x200>;
0062 /* filled by u-boot */
0063 bus-frequency = <0>;
0064
0065 wdt@200 {
0066 compatible = "mpc83xx_wdt";
0067 reg = <0x200 0x100>;
0068 };
0069
0070 pmc: power@b00 {
0071 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
0072 reg = <0xb00 0x100 0xa00 0x100>;
0073 interrupts = <80 0x8>;
0074 interrupt-parent = <&ipic>;
0075 };
0076
0077 i2c@3000 {
0078 #address-cells = <1>;
0079 #size-cells = <0>;
0080 cell-index = <0>;
0081 compatible = "fsl-i2c";
0082 reg = <0x3000 0x100>;
0083 interrupts = <14 8>;
0084 interrupt-parent = <&ipic>;
0085 dfsrr;
0086 };
0087
0088 i2c@3100 {
0089 #address-cells = <1>;
0090 #size-cells = <0>;
0091 cell-index = <1>;
0092 compatible = "fsl-i2c";
0093 reg = <0x3100 0x100>;
0094 interrupts = <16 8>;
0095 interrupt-parent = <&ipic>;
0096 dfsrr;
0097 };
0098
0099 serial0: serial@4500 {
0100 device_type = "serial";
0101 compatible = "fsl,ns16550", "ns16550";
0102 reg = <0x4500 0x100>;
0103 interrupts = <9 8>;
0104 interrupt-parent = <&ipic>;
0105 /* filled by u-boot */
0106 clock-frequency = <0>;
0107 };
0108
0109 serial1: serial@4600 {
0110 device_type = "serial";
0111 compatible = "fsl,ns16550", "ns16550";
0112 reg = <0x4600 0x100>;
0113 interrupts = <10 8>;
0114 interrupt-parent = <&ipic>;
0115 /* filled by u-boot */
0116 clock-frequency = <0>;
0117 };
0118
0119 dma@82a8 {
0120 #address-cells = <1>;
0121 #size-cells = <1>;
0122 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
0123 reg = <0x82a8 4>;
0124 ranges = <0 0x8100 0x1a8>;
0125 interrupt-parent = <&ipic>;
0126 interrupts = <71 8>;
0127 cell-index = <0>;
0128 dma-channel@0 {
0129 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0130 reg = <0 0x80>;
0131 cell-index = <0>;
0132 interrupt-parent = <&ipic>;
0133 interrupts = <71 8>;
0134 };
0135 dma-channel@80 {
0136 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0137 reg = <0x80 0x80>;
0138 cell-index = <1>;
0139 interrupt-parent = <&ipic>;
0140 interrupts = <71 8>;
0141 };
0142 dma-channel@100 {
0143 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0144 reg = <0x100 0x80>;
0145 cell-index = <2>;
0146 interrupt-parent = <&ipic>;
0147 interrupts = <71 8>;
0148 };
0149 dma-channel@180 {
0150 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0151 reg = <0x180 0x28>;
0152 cell-index = <3>;
0153 interrupt-parent = <&ipic>;
0154 interrupts = <71 8>;
0155 };
0156 };
0157
0158 crypto@30000 {
0159 compatible = "fsl,sec2.0";
0160 reg = <0x30000 0x10000>;
0161 interrupts = <11 0x8>;
0162 interrupt-parent = <&ipic>;
0163 fsl,num-channels = <4>;
0164 fsl,channel-fifo-len = <24>;
0165 fsl,exec-units-mask = <0x7e>;
0166 fsl,descriptor-types-mask = <0x01010ebf>;
0167 sleep = <&pmc 0x03000000>;
0168 };
0169
0170 ipic: interrupt-controller@700 {
0171 #address-cells = <0>;
0172 #interrupt-cells = <2>;
0173 compatible = "fsl,pq2pro-pic", "fsl,ipic";
0174 interrupt-controller;
0175 reg = <0x700 0x100>;
0176 };
0177
0178 qe_pio_b: gpio-controller@1418 {
0179 #gpio-cells = <2>;
0180 compatible = "fsl,mpc8360-qe-pario-bank",
0181 "fsl,mpc8323-qe-pario-bank";
0182 reg = <0x1418 0x18>;
0183 gpio-controller;
0184 };
0185
0186 qe_pio_e: gpio-controller@1460 {
0187 #gpio-cells = <2>;
0188 compatible = "fsl,mpc8360-qe-pario-bank",
0189 "fsl,mpc8323-qe-pario-bank";
0190 reg = <0x1460 0x18>;
0191 gpio-controller;
0192 };
0193
0194 qe@100000 {
0195 #address-cells = <1>;
0196 #size-cells = <1>;
0197 device_type = "qe";
0198 compatible = "fsl,qe", "simple-bus";
0199 ranges = <0 0x100000 0x100000>;
0200 reg = <0x100000 0x480>;
0201 /* filled by u-boot */
0202 clock-frequency = <0>;
0203 bus-frequency = <0>;
0204 brg-frequency = <0>;
0205 fsl,qe-num-riscs = <2>;
0206 fsl,qe-num-snums = <28>;
0207
0208 muram@10000 {
0209 #address-cells = <1>;
0210 #size-cells = <1>;
0211 compatible = "fsl,qe-muram", "fsl,cpm-muram";
0212 ranges = <0 0x10000 0xc000>;
0213
0214 data-only@0 {
0215 compatible = "fsl,qe-muram-data",
0216 "fsl,cpm-muram-data";
0217 reg = <0 0xc000>;
0218 };
0219 };
0220
0221 timer@440 {
0222 compatible = "fsl,mpc8360-qe-gtm",
0223 "fsl,qe-gtm", "fsl,gtm";
0224 reg = <0x440 0x40>;
0225 interrupts = <12 13 14 15>;
0226 interrupt-parent = <&qeic>;
0227 clock-frequency = <166666666>;
0228 };
0229
0230 usb@6c0 {
0231 compatible = "fsl,mpc8360-qe-usb",
0232 "fsl,mpc8323-qe-usb";
0233 reg = <0x6c0 0x40 0x8b00 0x100>;
0234 interrupts = <11>;
0235 interrupt-parent = <&qeic>;
0236 fsl,fullspeed-clock = "clk21";
0237 gpios = <&qe_pio_b 2 0 /* USBOE */
0238 &qe_pio_b 3 0 /* USBTP */
0239 &qe_pio_b 8 0 /* USBTN */
0240 &qe_pio_b 9 0 /* USBRP */
0241 &qe_pio_b 11 0 /* USBRN */
0242 &qe_pio_e 20 0 /* SPEED */
0243 &qe_pio_e 21 1 /* POWER */>;
0244 };
0245
0246 spi@4c0 {
0247 cell-index = <0>;
0248 compatible = "fsl,spi";
0249 reg = <0x4c0 0x40>;
0250 interrupts = <2>;
0251 interrupt-parent = <&qeic>;
0252 mode = "cpu-qe";
0253 };
0254
0255 spi@500 {
0256 cell-index = <1>;
0257 compatible = "fsl,spi";
0258 reg = <0x500 0x40>;
0259 interrupts = <1>;
0260 interrupt-parent = <&qeic>;
0261 mode = "cpu-qe";
0262 };
0263
0264 enet0: ucc@2000 {
0265 device_type = "network";
0266 compatible = "ucc_geth";
0267 cell-index = <1>;
0268 reg = <0x2000 0x200>;
0269 interrupts = <32>;
0270 interrupt-parent = <&qeic>;
0271 rx-clock-name = "none";
0272 tx-clock-name = "clk9";
0273 phy-handle = <&phy2>;
0274 phy-connection-type = "rgmii-rxid";
0275 /* filled by u-boot */
0276 local-mac-address = [ 00 00 00 00 00 00 ];
0277 };
0278
0279 enet1: ucc@3000 {
0280 device_type = "network";
0281 compatible = "ucc_geth";
0282 cell-index = <2>;
0283 reg = <0x3000 0x200>;
0284 interrupts = <33>;
0285 interrupt-parent = <&qeic>;
0286 rx-clock-name = "none";
0287 tx-clock-name = "clk4";
0288 phy-handle = <&phy4>;
0289 phy-connection-type = "rgmii-rxid";
0290 /* filled by u-boot */
0291 local-mac-address = [ 00 00 00 00 00 00 ];
0292 };
0293
0294 enet2: ucc@2600 {
0295 device_type = "network";
0296 compatible = "ucc_geth";
0297 cell-index = <7>;
0298 reg = <0x2600 0x200>;
0299 interrupts = <42>;
0300 interrupt-parent = <&qeic>;
0301 rx-clock-name = "clk20";
0302 tx-clock-name = "clk19";
0303 phy-handle = <&phy1>;
0304 phy-connection-type = "mii";
0305 /* filled by u-boot */
0306 local-mac-address = [ 00 00 00 00 00 00 ];
0307 };
0308
0309 enet3: ucc@3200 {
0310 device_type = "network";
0311 compatible = "ucc_geth";
0312 cell-index = <4>;
0313 reg = <0x3200 0x200>;
0314 interrupts = <35>;
0315 interrupt-parent = <&qeic>;
0316 rx-clock-name = "clk8";
0317 tx-clock-name = "clk7";
0318 phy-handle = <&phy3>;
0319 phy-connection-type = "mii";
0320 /* filled by u-boot */
0321 local-mac-address = [ 00 00 00 00 00 00 ];
0322 };
0323
0324 mdio@2120 {
0325 #address-cells = <1>;
0326 #size-cells = <0>;
0327 compatible = "fsl,ucc-mdio";
0328 reg = <0x2120 0x18>;
0329
0330 phy1: ethernet-phy@1 {
0331 compatible = "national,DP83848VV";
0332 reg = <1>;
0333 };
0334
0335 phy2: ethernet-phy@2 {
0336 compatible = "broadcom,BCM5481UA2KMLG";
0337 reg = <2>;
0338 };
0339
0340 phy3: ethernet-phy@3 {
0341 compatible = "national,DP83848VV";
0342 reg = <3>;
0343 };
0344
0345 phy4: ethernet-phy@4 {
0346 compatible = "broadcom,BCM5481UA2KMLG";
0347 reg = <4>;
0348 };
0349 };
0350
0351 serial2: ucc@2400 {
0352 device_type = "serial";
0353 compatible = "ucc_uart";
0354 reg = <0x2400 0x200>;
0355 cell-index = <5>;
0356 port-number = <0>;
0357 rx-clock-name = "brg7";
0358 tx-clock-name = "brg8";
0359 interrupts = <40>;
0360 interrupt-parent = <&qeic>;
0361 soft-uart;
0362 };
0363
0364 serial3: ucc@3400 {
0365 device_type = "serial";
0366 compatible = "ucc_uart";
0367 reg = <0x3400 0x200>;
0368 cell-index = <6>;
0369 port-number = <1>;
0370 rx-clock-name = "brg13";
0371 tx-clock-name = "brg14";
0372 interrupts = <41>;
0373 interrupt-parent = <&qeic>;
0374 soft-uart;
0375 };
0376
0377 qeic: interrupt-controller@80 {
0378 #address-cells = <0>;
0379 #interrupt-cells = <1>;
0380 compatible = "fsl,qe-ic";
0381 interrupt-controller;
0382 reg = <0x80 0x80>;
0383 big-endian;
0384 interrupts = <32 8 33 8>;
0385 interrupt-parent = <&ipic>;
0386 };
0387 };
0388 };
0389
0390 localbus@e0005000 {
0391 #address-cells = <2>;
0392 #size-cells = <1>;
0393 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
0394 "simple-bus";
0395 reg = <0xe0005000 0xd8>;
0396 ranges = <0 0 0xff800000 0x0800000
0397 1 0 0x60000000 0x0001000
0398 2 0 0x70000000 0x4000000>;
0399
0400 flash@0,0 {
0401 compatible = "intel,PC28F640P30T85", "cfi-flash";
0402 reg = <0 0 0x800000>;
0403 bank-width = <2>;
0404 device-width = <1>;
0405 };
0406
0407 upm@1,0 {
0408 compatible = "fsl,upm-nand";
0409 reg = <1 0 1>;
0410 fsl,upm-addr-offset = <16>;
0411 fsl,upm-cmd-offset = <8>;
0412 gpios = <&qe_pio_e 18 0>;
0413
0414 flash {
0415 compatible = "st,nand512-a";
0416 };
0417 };
0418
0419 display@2,0 {
0420 device_type = "display";
0421 compatible = "fujitsu,MB86277", "fujitsu,mint";
0422 reg = <2 0 0x4000000>;
0423 fujitsu,sh3;
0424 little-endian;
0425 /* filled by u-boot */
0426 address = <0>;
0427 depth = <0>;
0428 width = <0>;
0429 height = <0>;
0430 linebytes = <0>;
0431 /* linux,opened; - added by uboot */
0432 };
0433 };
0434
0435 pci0: pci@e0008500 {
0436 #address-cells = <3>;
0437 #size-cells = <2>;
0438 #interrupt-cells = <1>;
0439 device_type = "pci";
0440 compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci";
0441 reg = <0xe0008500 0x100 /* internal registers */
0442 0xe0008300 0x8>; /* config space access registers */
0443 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
0444 0x42000000 0 0x80000000 0x80000000 0 0x10000000
0445 0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>;
0446 interrupts = <66 8>;
0447 interrupt-parent = <&ipic>;
0448 interrupt-map-mask = <0xf800 0 0 7>;
0449 interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */
0450 0xa000 0 0 1 &ipic 18 8
0451 0xa000 0 0 2 &ipic 19 8
0452
0453 /* PCI1 IDSEL 0x15 AD21 */
0454 0xa800 0 0 1 &ipic 19 8
0455 0xa800 0 0 2 &ipic 20 8
0456 0xa800 0 0 3 &ipic 21 8
0457 0xa800 0 0 4 &ipic 18 8>;
0458 sleep = <&pmc 0x00010000>;
0459 /* filled by u-boot */
0460 bus-range = <0 0>;
0461 clock-frequency = <0>;
0462 };
0463 };
