0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8360E EMDS Device Tree Source
0004 *
0005 * Copyright 2006 Freescale Semiconductor Inc.
0006 */
0007
0008
0009 /*
0010 /memreserve/ 00000000 1000000;
0011 */
0012
0013 /dts-v1/;
0014
0015 / {
0016 model = "MPC8360MDS";
0017 compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
0018 #address-cells = <1>;
0019 #size-cells = <1>;
0020
0021 aliases {
0022 ethernet0 = &enet0;
0023 ethernet1 = &enet1;
0024 serial0 = &serial0;
0025 serial1 = &serial1;
0026 pci0 = &pci0;
0027 };
0028
0029 cpus {
0030 #address-cells = <1>;
0031 #size-cells = <0>;
0032
0033 PowerPC,8360@0 {
0034 device_type = "cpu";
0035 reg = <0x0>;
0036 d-cache-line-size = <32>; // 32 bytes
0037 i-cache-line-size = <32>; // 32 bytes
0038 d-cache-size = <32768>; // L1, 32K
0039 i-cache-size = <32768>; // L1, 32K
0040 timebase-frequency = <66000000>;
0041 bus-frequency = <264000000>;
0042 clock-frequency = <528000000>;
0043 };
0044 };
0045
0046 memory {
0047 device_type = "memory";
0048 reg = <0x00000000 0x10000000>;
0049 };
0050
0051 localbus@e0005000 {
0052 #address-cells = <2>;
0053 #size-cells = <1>;
0054 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
0055 "simple-bus";
0056 reg = <0xe0005000 0xd8>;
0057 ranges = <0 0 0xfe000000 0x02000000
0058 1 0 0xf8000000 0x00008000>;
0059
0060 flash@0,0 {
0061 compatible = "cfi-flash";
0062 reg = <0 0 0x2000000>;
0063 bank-width = <2>;
0064 device-width = <1>;
0065 };
0066
0067 bcsr@1,0 {
0068 #address-cells = <1>;
0069 #size-cells = <1>;
0070 compatible = "fsl,mpc8360mds-bcsr";
0071 reg = <1 0 0x8000>;
0072 ranges = <0 1 0 0x8000>;
0073
0074 bcsr13: gpio-controller@d {
0075 #gpio-cells = <2>;
0076 compatible = "fsl,mpc8360mds-bcsr-gpio";
0077 reg = <0xd 1>;
0078 gpio-controller;
0079 };
0080 };
0081 };
0082
0083 soc8360@e0000000 {
0084 #address-cells = <1>;
0085 #size-cells = <1>;
0086 device_type = "soc";
0087 compatible = "simple-bus";
0088 ranges = <0x0 0xe0000000 0x00100000>;
0089 reg = <0xe0000000 0x00000200>;
0090 bus-frequency = <264000000>;
0091
0092 wdt@200 {
0093 device_type = "watchdog";
0094 compatible = "mpc83xx_wdt";
0095 reg = <0x200 0x100>;
0096 };
0097
0098 pmc: power@b00 {
0099 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
0100 reg = <0xb00 0x100 0xa00 0x100>;
0101 interrupts = <80 0x8>;
0102 interrupt-parent = <&ipic>;
0103 };
0104
0105 i2c@3000 {
0106 #address-cells = <1>;
0107 #size-cells = <0>;
0108 cell-index = <0>;
0109 compatible = "fsl-i2c";
0110 reg = <0x3000 0x100>;
0111 interrupts = <14 0x8>;
0112 interrupt-parent = <&ipic>;
0113 dfsrr;
0114
0115 rtc@68 {
0116 compatible = "dallas,ds1374";
0117 reg = <0x68>;
0118 };
0119 };
0120
0121 i2c@3100 {
0122 #address-cells = <1>;
0123 #size-cells = <0>;
0124 cell-index = <1>;
0125 compatible = "fsl-i2c";
0126 reg = <0x3100 0x100>;
0127 interrupts = <15 0x8>;
0128 interrupt-parent = <&ipic>;
0129 dfsrr;
0130 };
0131
0132 serial0: serial@4500 {
0133 cell-index = <0>;
0134 device_type = "serial";
0135 compatible = "fsl,ns16550", "ns16550";
0136 reg = <0x4500 0x100>;
0137 clock-frequency = <264000000>;
0138 interrupts = <9 0x8>;
0139 interrupt-parent = <&ipic>;
0140 };
0141
0142 serial1: serial@4600 {
0143 cell-index = <1>;
0144 device_type = "serial";
0145 compatible = "fsl,ns16550", "ns16550";
0146 reg = <0x4600 0x100>;
0147 clock-frequency = <264000000>;
0148 interrupts = <10 0x8>;
0149 interrupt-parent = <&ipic>;
0150 };
0151
0152 dma@82a8 {
0153 #address-cells = <1>;
0154 #size-cells = <1>;
0155 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
0156 reg = <0x82a8 4>;
0157 ranges = <0 0x8100 0x1a8>;
0158 interrupt-parent = <&ipic>;
0159 interrupts = <71 8>;
0160 cell-index = <0>;
0161 dma-channel@0 {
0162 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0163 reg = <0 0x80>;
0164 cell-index = <0>;
0165 interrupt-parent = <&ipic>;
0166 interrupts = <71 8>;
0167 };
0168 dma-channel@80 {
0169 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0170 reg = <0x80 0x80>;
0171 cell-index = <1>;
0172 interrupt-parent = <&ipic>;
0173 interrupts = <71 8>;
0174 };
0175 dma-channel@100 {
0176 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0177 reg = <0x100 0x80>;
0178 cell-index = <2>;
0179 interrupt-parent = <&ipic>;
0180 interrupts = <71 8>;
0181 };
0182 dma-channel@180 {
0183 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0184 reg = <0x180 0x28>;
0185 cell-index = <3>;
0186 interrupt-parent = <&ipic>;
0187 interrupts = <71 8>;
0188 };
0189 };
0190
0191 crypto@30000 {
0192 compatible = "fsl,sec2.0";
0193 reg = <0x30000 0x10000>;
0194 interrupts = <11 0x8>;
0195 interrupt-parent = <&ipic>;
0196 fsl,num-channels = <4>;
0197 fsl,channel-fifo-len = <24>;
0198 fsl,exec-units-mask = <0x7e>;
0199 fsl,descriptor-types-mask = <0x01010ebf>;
0200 sleep = <&pmc 0x03000000>;
0201 };
0202
0203 ipic: pic@700 {
0204 interrupt-controller;
0205 #address-cells = <0>;
0206 #interrupt-cells = <2>;
0207 reg = <0x700 0x100>;
0208 device_type = "ipic";
0209 };
0210
0211 par_io@1400 {
0212 #address-cells = <1>;
0213 #size-cells = <1>;
0214 reg = <0x1400 0x100>;
0215 ranges = <0 0x1400 0x100>;
0216 device_type = "par_io";
0217 num-ports = <7>;
0218
0219 qe_pio_b: gpio-controller@18 {
0220 #gpio-cells = <2>;
0221 compatible = "fsl,mpc8360-qe-pario-bank",
0222 "fsl,mpc8323-qe-pario-bank";
0223 reg = <0x18 0x18>;
0224 gpio-controller;
0225 };
0226
0227 pio1: ucc_pin@1 {
0228 pio-map = <
0229 /* port pin dir open_drain assignment has_irq */
0230 0 3 1 0 1 0 /* TxD0 */
0231 0 4 1 0 1 0 /* TxD1 */
0232 0 5 1 0 1 0 /* TxD2 */
0233 0 6 1 0 1 0 /* TxD3 */
0234 1 6 1 0 3 0 /* TxD4 */
0235 1 7 1 0 1 0 /* TxD5 */
0236 1 9 1 0 2 0 /* TxD6 */
0237 1 10 1 0 2 0 /* TxD7 */
0238 0 9 2 0 1 0 /* RxD0 */
0239 0 10 2 0 1 0 /* RxD1 */
0240 0 11 2 0 1 0 /* RxD2 */
0241 0 12 2 0 1 0 /* RxD3 */
0242 0 13 2 0 1 0 /* RxD4 */
0243 1 1 2 0 2 0 /* RxD5 */
0244 1 0 2 0 2 0 /* RxD6 */
0245 1 4 2 0 2 0 /* RxD7 */
0246 0 7 1 0 1 0 /* TX_EN */
0247 0 8 1 0 1 0 /* TX_ER */
0248 0 15 2 0 1 0 /* RX_DV */
0249 0 16 2 0 1 0 /* RX_ER */
0250 0 0 2 0 1 0 /* RX_CLK */
0251 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
0252 2 8 2 0 1 0>; /* GTX125 - CLK9 */
0253 };
0254 pio2: ucc_pin@2 {
0255 pio-map = <
0256 /* port pin dir open_drain assignment has_irq */
0257 0 17 1 0 1 0 /* TxD0 */
0258 0 18 1 0 1 0 /* TxD1 */
0259 0 19 1 0 1 0 /* TxD2 */
0260 0 20 1 0 1 0 /* TxD3 */
0261 1 2 1 0 1 0 /* TxD4 */
0262 1 3 1 0 2 0 /* TxD5 */
0263 1 5 1 0 3 0 /* TxD6 */
0264 1 8 1 0 3 0 /* TxD7 */
0265 0 23 2 0 1 0 /* RxD0 */
0266 0 24 2 0 1 0 /* RxD1 */
0267 0 25 2 0 1 0 /* RxD2 */
0268 0 26 2 0 1 0 /* RxD3 */
0269 0 27 2 0 1 0 /* RxD4 */
0270 1 12 2 0 2 0 /* RxD5 */
0271 1 13 2 0 3 0 /* RxD6 */
0272 1 11 2 0 2 0 /* RxD7 */
0273 0 21 1 0 1 0 /* TX_EN */
0274 0 22 1 0 1 0 /* TX_ER */
0275 0 29 2 0 1 0 /* RX_DV */
0276 0 30 2 0 1 0 /* RX_ER */
0277 0 31 2 0 1 0 /* RX_CLK */
0278 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
0279 2 3 2 0 1 0 /* GTX125 - CLK4 */
0280 0 1 3 0 2 0 /* MDIO */
0281 0 2 1 0 1 0>; /* MDC */
0282 };
0283
0284 };
0285 };
0286
0287 qe@e0100000 {
0288 #address-cells = <1>;
0289 #size-cells = <1>;
0290 device_type = "qe";
0291 compatible = "fsl,qe";
0292 ranges = <0x0 0xe0100000 0x00100000>;
0293 reg = <0xe0100000 0x480>;
0294 brg-frequency = <0>;
0295 bus-frequency = <396000000>;
0296 fsl,qe-num-riscs = <2>;
0297 fsl,qe-num-snums = <28>;
0298
0299 muram@10000 {
0300 #address-cells = <1>;
0301 #size-cells = <1>;
0302 compatible = "fsl,qe-muram", "fsl,cpm-muram";
0303 ranges = <0x0 0x00010000 0x0000c000>;
0304
0305 data-only@0 {
0306 compatible = "fsl,qe-muram-data",
0307 "fsl,cpm-muram-data";
0308 reg = <0x0 0xc000>;
0309 };
0310 };
0311
0312 timer@440 {
0313 compatible = "fsl,mpc8360-qe-gtm",
0314 "fsl,qe-gtm", "fsl,gtm";
0315 reg = <0x440 0x40>;
0316 clock-frequency = <132000000>;
0317 interrupts = <12 13 14 15>;
0318 interrupt-parent = <&qeic>;
0319 };
0320
0321 spi@4c0 {
0322 cell-index = <0>;
0323 compatible = "fsl,spi";
0324 reg = <0x4c0 0x40>;
0325 interrupts = <2>;
0326 interrupt-parent = <&qeic>;
0327 mode = "cpu";
0328 };
0329
0330 spi@500 {
0331 cell-index = <1>;
0332 compatible = "fsl,spi";
0333 reg = <0x500 0x40>;
0334 interrupts = <1>;
0335 interrupt-parent = <&qeic>;
0336 mode = "cpu";
0337 };
0338
0339 usb@6c0 {
0340 compatible = "fsl,mpc8360-qe-usb",
0341 "fsl,mpc8323-qe-usb";
0342 reg = <0x6c0 0x40 0x8b00 0x100>;
0343 interrupts = <11>;
0344 interrupt-parent = <&qeic>;
0345 fsl,fullspeed-clock = "clk21";
0346 fsl,lowspeed-clock = "brg9";
0347 gpios = <&qe_pio_b 2 0 /* USBOE */
0348 &qe_pio_b 3 0 /* USBTP */
0349 &qe_pio_b 8 0 /* USBTN */
0350 &qe_pio_b 9 0 /* USBRP */
0351 &qe_pio_b 11 0 /* USBRN */
0352 &bcsr13 5 0 /* SPEED */
0353 &bcsr13 4 1>; /* POWER */
0354 };
0355
0356 enet0: ucc@2000 {
0357 device_type = "network";
0358 compatible = "ucc_geth";
0359 cell-index = <1>;
0360 reg = <0x2000 0x200>;
0361 interrupts = <32>;
0362 interrupt-parent = <&qeic>;
0363 local-mac-address = [ 00 00 00 00 00 00 ];
0364 rx-clock-name = "none";
0365 tx-clock-name = "clk9";
0366 phy-handle = <&phy0>;
0367 phy-connection-type = "rgmii-id";
0368 pio-handle = <&pio1>;
0369 };
0370
0371 enet1: ucc@3000 {
0372 device_type = "network";
0373 compatible = "ucc_geth";
0374 cell-index = <2>;
0375 reg = <0x3000 0x200>;
0376 interrupts = <33>;
0377 interrupt-parent = <&qeic>;
0378 local-mac-address = [ 00 00 00 00 00 00 ];
0379 rx-clock-name = "none";
0380 tx-clock-name = "clk4";
0381 phy-handle = <&phy1>;
0382 phy-connection-type = "rgmii-id";
0383 pio-handle = <&pio2>;
0384 };
0385
0386 mdio@2120 {
0387 #address-cells = <1>;
0388 #size-cells = <0>;
0389 reg = <0x2120 0x18>;
0390 compatible = "fsl,ucc-mdio";
0391
0392 phy0: ethernet-phy@0 {
0393 interrupt-parent = <&ipic>;
0394 interrupts = <17 0x8>;
0395 reg = <0x0>;
0396 };
0397 phy1: ethernet-phy@1 {
0398 interrupt-parent = <&ipic>;
0399 interrupts = <18 0x8>;
0400 reg = <0x1>;
0401 };
0402 tbi-phy@2 {
0403 device_type = "tbi-phy";
0404 reg = <0x2>;
0405 };
0406 };
0407
0408 qeic: interrupt-controller@80 {
0409 interrupt-controller;
0410 compatible = "fsl,qe-ic";
0411 #address-cells = <0>;
0412 #interrupt-cells = <1>;
0413 reg = <0x80 0x80>;
0414 big-endian;
0415 interrupts = <32 0x8 33 0x8>; // high:32 low:33
0416 interrupt-parent = <&ipic>;
0417 };
0418 };
0419
0420 pci0: pci@e0008500 {
0421 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0422 interrupt-map = <
0423
0424 /* IDSEL 0x11 AD17 */
0425 0x8800 0x0 0x0 0x1 &ipic 20 0x8
0426 0x8800 0x0 0x0 0x2 &ipic 21 0x8
0427 0x8800 0x0 0x0 0x3 &ipic 22 0x8
0428 0x8800 0x0 0x0 0x4 &ipic 23 0x8
0429
0430 /* IDSEL 0x12 AD18 */
0431 0x9000 0x0 0x0 0x1 &ipic 22 0x8
0432 0x9000 0x0 0x0 0x2 &ipic 23 0x8
0433 0x9000 0x0 0x0 0x3 &ipic 20 0x8
0434 0x9000 0x0 0x0 0x4 &ipic 21 0x8
0435
0436 /* IDSEL 0x13 AD19 */
0437 0x9800 0x0 0x0 0x1 &ipic 23 0x8
0438 0x9800 0x0 0x0 0x2 &ipic 20 0x8
0439 0x9800 0x0 0x0 0x3 &ipic 21 0x8
0440 0x9800 0x0 0x0 0x4 &ipic 22 0x8
0441
0442 /* IDSEL 0x15 AD21*/
0443 0xa800 0x0 0x0 0x1 &ipic 20 0x8
0444 0xa800 0x0 0x0 0x2 &ipic 21 0x8
0445 0xa800 0x0 0x0 0x3 &ipic 22 0x8
0446 0xa800 0x0 0x0 0x4 &ipic 23 0x8
0447
0448 /* IDSEL 0x16 AD22*/
0449 0xb000 0x0 0x0 0x1 &ipic 23 0x8
0450 0xb000 0x0 0x0 0x2 &ipic 20 0x8
0451 0xb000 0x0 0x0 0x3 &ipic 21 0x8
0452 0xb000 0x0 0x0 0x4 &ipic 22 0x8
0453
0454 /* IDSEL 0x17 AD23*/
0455 0xb800 0x0 0x0 0x1 &ipic 22 0x8
0456 0xb800 0x0 0x0 0x2 &ipic 23 0x8
0457 0xb800 0x0 0x0 0x3 &ipic 20 0x8
0458 0xb800 0x0 0x0 0x4 &ipic 21 0x8
0459
0460 /* IDSEL 0x18 AD24*/
0461 0xc000 0x0 0x0 0x1 &ipic 21 0x8
0462 0xc000 0x0 0x0 0x2 &ipic 22 0x8
0463 0xc000 0x0 0x0 0x3 &ipic 23 0x8
0464 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
0465 interrupt-parent = <&ipic>;
0466 interrupts = <66 0x8>;
0467 bus-range = <0 0>;
0468 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0469 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0470 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
0471 clock-frequency = <66666666>;
0472 #interrupt-cells = <1>;
0473 #size-cells = <2>;
0474 #address-cells = <3>;
0475 reg = <0xe0008500 0x100 /* internal registers */
0476 0xe0008300 0x8>; /* config space access registers */
0477 compatible = "fsl,mpc8349-pci";
0478 device_type = "pci";
0479 sleep = <&pmc 0x00010000>;
0480 };
0481 };
