0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC832x RDB Device Tree Source
0004 *
0005 * Copyright 2007 Freescale Semiconductor Inc.
0006 */
0007
0008 /dts-v1/;
0009
0010 / {
0011 model = "MPC8323ERDB";
0012 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 aliases {
0017 ethernet0 = &enet1;
0018 ethernet1 = &enet0;
0019 serial0 = &serial0;
0020 serial1 = &serial1;
0021 pci0 = &pci0;
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 PowerPC,8323@0 {
0029 device_type = "cpu";
0030 reg = <0x0>;
0031 d-cache-line-size = <0x20>; // 32 bytes
0032 i-cache-line-size = <0x20>; // 32 bytes
0033 d-cache-size = <16384>; // L1, 16K
0034 i-cache-size = <16384>; // L1, 16K
0035 timebase-frequency = <0>;
0036 bus-frequency = <0>;
0037 clock-frequency = <0>;
0038 };
0039 };
0040
0041 memory {
0042 device_type = "memory";
0043 reg = <0x00000000 0x04000000>;
0044 };
0045
0046 soc8323@e0000000 {
0047 #address-cells = <1>;
0048 #size-cells = <1>;
0049 device_type = "soc";
0050 compatible = "simple-bus";
0051 ranges = <0x0 0xe0000000 0x00100000>;
0052 reg = <0xe0000000 0x00000200>;
0053 bus-frequency = <0>;
0054
0055 wdt@200 {
0056 device_type = "watchdog";
0057 compatible = "mpc83xx_wdt";
0058 reg = <0x200 0x100>;
0059 };
0060
0061 pmc: power@b00 {
0062 compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
0063 reg = <0xb00 0x100 0xa00 0x100>;
0064 interrupts = <80 0x8>;
0065 interrupt-parent = <&ipic>;
0066 };
0067
0068 i2c@3000 {
0069 #address-cells = <1>;
0070 #size-cells = <0>;
0071 cell-index = <0>;
0072 compatible = "fsl-i2c";
0073 reg = <0x3000 0x100>;
0074 interrupts = <14 0x8>;
0075 interrupt-parent = <&ipic>;
0076 dfsrr;
0077 };
0078
0079 serial0: serial@4500 {
0080 cell-index = <0>;
0081 device_type = "serial";
0082 compatible = "fsl,ns16550", "ns16550";
0083 reg = <0x4500 0x100>;
0084 clock-frequency = <0>;
0085 interrupts = <9 0x8>;
0086 interrupt-parent = <&ipic>;
0087 };
0088
0089 serial1: serial@4600 {
0090 cell-index = <1>;
0091 device_type = "serial";
0092 compatible = "fsl,ns16550", "ns16550";
0093 reg = <0x4600 0x100>;
0094 clock-frequency = <0>;
0095 interrupts = <10 0x8>;
0096 interrupt-parent = <&ipic>;
0097 };
0098
0099 dma@82a8 {
0100 #address-cells = <1>;
0101 #size-cells = <1>;
0102 compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
0103 reg = <0x82a8 4>;
0104 ranges = <0 0x8100 0x1a8>;
0105 interrupt-parent = <&ipic>;
0106 interrupts = <71 8>;
0107 cell-index = <0>;
0108 dma-channel@0 {
0109 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
0110 reg = <0 0x80>;
0111 cell-index = <0>;
0112 interrupt-parent = <&ipic>;
0113 interrupts = <71 8>;
0114 };
0115 dma-channel@80 {
0116 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
0117 reg = <0x80 0x80>;
0118 cell-index = <1>;
0119 interrupt-parent = <&ipic>;
0120 interrupts = <71 8>;
0121 };
0122 dma-channel@100 {
0123 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
0124 reg = <0x100 0x80>;
0125 cell-index = <2>;
0126 interrupt-parent = <&ipic>;
0127 interrupts = <71 8>;
0128 };
0129 dma-channel@180 {
0130 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
0131 reg = <0x180 0x28>;
0132 cell-index = <3>;
0133 interrupt-parent = <&ipic>;
0134 interrupts = <71 8>;
0135 };
0136 };
0137
0138 crypto@30000 {
0139 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
0140 reg = <0x30000 0x10000>;
0141 interrupts = <11 0x8>;
0142 interrupt-parent = <&ipic>;
0143 fsl,num-channels = <1>;
0144 fsl,channel-fifo-len = <24>;
0145 fsl,exec-units-mask = <0x4c>;
0146 fsl,descriptor-types-mask = <0x0122003f>;
0147 sleep = <&pmc 0x03000000>;
0148 };
0149
0150 ipic:pic@700 {
0151 interrupt-controller;
0152 #address-cells = <0>;
0153 #interrupt-cells = <2>;
0154 reg = <0x700 0x100>;
0155 device_type = "ipic";
0156 };
0157
0158 par_io@1400 {
0159 #address-cells = <1>;
0160 #size-cells = <1>;
0161 reg = <0x1400 0x100>;
0162 ranges = <3 0x1448 0x18>;
0163 compatible = "fsl,mpc8323-qe-pario";
0164 device_type = "par_io";
0165 num-ports = <7>;
0166
0167 qe_pio_d: gpio-controller@1448 {
0168 #gpio-cells = <2>;
0169 compatible = "fsl,mpc8323-qe-pario-bank";
0170 reg = <3 0x18>;
0171 gpio-controller;
0172 };
0173
0174 ucc2pio:ucc_pin@2 {
0175 pio-map = <
0176 /* port pin dir open_drain assignment has_irq */
0177 3 4 3 0 2 0 /* MDIO */
0178 3 5 1 0 2 0 /* MDC */
0179 3 21 2 0 1 0 /* RX_CLK (CLK16) */
0180 3 23 2 0 1 0 /* TX_CLK (CLK3) */
0181 0 18 1 0 1 0 /* TxD0 */
0182 0 19 1 0 1 0 /* TxD1 */
0183 0 20 1 0 1 0 /* TxD2 */
0184 0 21 1 0 1 0 /* TxD3 */
0185 0 22 2 0 1 0 /* RxD0 */
0186 0 23 2 0 1 0 /* RxD1 */
0187 0 24 2 0 1 0 /* RxD2 */
0188 0 25 2 0 1 0 /* RxD3 */
0189 0 26 2 0 1 0 /* RX_ER */
0190 0 27 1 0 1 0 /* TX_ER */
0191 0 28 2 0 1 0 /* RX_DV */
0192 0 29 2 0 1 0 /* COL */
0193 0 30 1 0 1 0 /* TX_EN */
0194 0 31 2 0 1 0>; /* CRS */
0195 };
0196 ucc3pio:ucc_pin@3 {
0197 pio-map = <
0198 /* port pin dir open_drain assignment has_irq */
0199 0 13 2 0 1 0 /* RX_CLK (CLK9) */
0200 3 24 2 0 1 0 /* TX_CLK (CLK10) */
0201 1 0 1 0 1 0 /* TxD0 */
0202 1 1 1 0 1 0 /* TxD1 */
0203 1 2 1 0 1 0 /* TxD2 */
0204 1 3 1 0 1 0 /* TxD3 */
0205 1 4 2 0 1 0 /* RxD0 */
0206 1 5 2 0 1 0 /* RxD1 */
0207 1 6 2 0 1 0 /* RxD2 */
0208 1 7 2 0 1 0 /* RxD3 */
0209 1 8 2 0 1 0 /* RX_ER */
0210 1 9 1 0 1 0 /* TX_ER */
0211 1 10 2 0 1 0 /* RX_DV */
0212 1 11 2 0 1 0 /* COL */
0213 1 12 1 0 1 0 /* TX_EN */
0214 1 13 2 0 1 0>; /* CRS */
0215 };
0216 };
0217 };
0218
0219 qe@e0100000 {
0220 #address-cells = <1>;
0221 #size-cells = <1>;
0222 device_type = "qe";
0223 compatible = "fsl,qe";
0224 ranges = <0x0 0xe0100000 0x00100000>;
0225 reg = <0xe0100000 0x480>;
0226 brg-frequency = <0>;
0227 bus-frequency = <198000000>;
0228 fsl,qe-num-riscs = <1>;
0229 fsl,qe-num-snums = <28>;
0230
0231 muram@10000 {
0232 #address-cells = <1>;
0233 #size-cells = <1>;
0234 compatible = "fsl,qe-muram", "fsl,cpm-muram";
0235 ranges = <0x0 0x00010000 0x00004000>;
0236
0237 data-only@0 {
0238 compatible = "fsl,qe-muram-data",
0239 "fsl,cpm-muram-data";
0240 reg = <0x0 0x4000>;
0241 };
0242 };
0243
0244 spi@4c0 {
0245 #address-cells = <1>;
0246 #size-cells = <0>;
0247 cell-index = <0>;
0248 compatible = "fsl,spi";
0249 reg = <0x4c0 0x40>;
0250 interrupts = <2>;
0251 interrupt-parent = <&qeic>;
0252 cs-gpios = <&qe_pio_d 13 0>;
0253 mode = "cpu-qe";
0254
0255 mmc-slot@0 {
0256 compatible = "fsl,mpc8323rdb-mmc-slot",
0257 "mmc-spi-slot";
0258 reg = <0>;
0259 gpios = <&qe_pio_d 14 1
0260 &qe_pio_d 15 0>;
0261 voltage-ranges = <3300 3300>;
0262 spi-max-frequency = <50000000>;
0263 };
0264 };
0265
0266 spi@500 {
0267 cell-index = <1>;
0268 compatible = "fsl,spi";
0269 reg = <0x500 0x40>;
0270 interrupts = <1>;
0271 interrupt-parent = <&qeic>;
0272 mode = "cpu";
0273 };
0274
0275 enet0: ucc@3000 {
0276 device_type = "network";
0277 compatible = "ucc_geth";
0278 cell-index = <2>;
0279 reg = <0x3000 0x200>;
0280 interrupts = <33>;
0281 interrupt-parent = <&qeic>;
0282 local-mac-address = [ 00 00 00 00 00 00 ];
0283 rx-clock-name = "clk16";
0284 tx-clock-name = "clk3";
0285 phy-handle = <&phy00>;
0286 pio-handle = <&ucc2pio>;
0287 };
0288
0289 enet1: ucc@2200 {
0290 device_type = "network";
0291 compatible = "ucc_geth";
0292 cell-index = <3>;
0293 reg = <0x2200 0x200>;
0294 interrupts = <34>;
0295 interrupt-parent = <&qeic>;
0296 local-mac-address = [ 00 00 00 00 00 00 ];
0297 rx-clock-name = "clk9";
0298 tx-clock-name = "clk10";
0299 phy-handle = <&phy04>;
0300 pio-handle = <&ucc3pio>;
0301 };
0302
0303 mdio@3120 {
0304 #address-cells = <1>;
0305 #size-cells = <0>;
0306 reg = <0x3120 0x18>;
0307 compatible = "fsl,ucc-mdio";
0308
0309 phy00:ethernet-phy@0 {
0310 reg = <0x0>;
0311 };
0312 phy04:ethernet-phy@4 {
0313 reg = <0x4>;
0314 };
0315 };
0316
0317 qeic:interrupt-controller@80 {
0318 interrupt-controller;
0319 compatible = "fsl,qe-ic";
0320 #address-cells = <0>;
0321 #interrupt-cells = <1>;
0322 reg = <0x80 0x80>;
0323 big-endian;
0324 interrupts = <32 0x8 33 0x8>; //high:32 low:33
0325 interrupt-parent = <&ipic>;
0326 };
0327 };
0328
0329 pci0: pci@e0008500 {
0330 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0331 interrupt-map = <
0332 /* IDSEL 0x10 AD16 (USB) */
0333 0x8000 0x0 0x0 0x1 &ipic 17 0x8
0334
0335 /* IDSEL 0x11 AD17 (Mini1)*/
0336 0x8800 0x0 0x0 0x1 &ipic 18 0x8
0337 0x8800 0x0 0x0 0x2 &ipic 19 0x8
0338 0x8800 0x0 0x0 0x3 &ipic 20 0x8
0339 0x8800 0x0 0x0 0x4 &ipic 48 0x8
0340
0341 /* IDSEL 0x12 AD18 (PCI/Mini2) */
0342 0x9000 0x0 0x0 0x1 &ipic 19 0x8
0343 0x9000 0x0 0x0 0x2 &ipic 20 0x8
0344 0x9000 0x0 0x0 0x3 &ipic 48 0x8
0345 0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
0346
0347 interrupt-parent = <&ipic>;
0348 interrupts = <66 0x8>;
0349 bus-range = <0x0 0x0>;
0350 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0351 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0352 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
0353 clock-frequency = <0>;
0354 #interrupt-cells = <1>;
0355 #size-cells = <2>;
0356 #address-cells = <3>;
0357 reg = <0xe0008500 0x100 /* internal registers */
0358 0xe0008300 0x8>; /* config space access registers */
0359 compatible = "fsl,mpc8349-pci";
0360 device_type = "pci";
0361 sleep = <&pmc 0x00010000>;
0362 };
0363 };
