0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8323E EMDS Device Tree Source
0004 *
0005 * Copyright 2006 Freescale Semiconductor Inc.
0006 *
0007
0008 * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
0009 * this:
0010 *
0011 * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
0012 * 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
0013 * next to the serial ports.
0014 * 3) Solder a wire from U61-22 to P19K-22.
0015 *
0016 * Note that there's a typo in the schematic. The board labels the last column
0017 * of pins "P19K", but in the schematic, that column is called "P19J". So if
0018 * you're going by the schematic, the pin is called "P19J-K22".
0019 */
0020
0021 /dts-v1/;
0022
0023 / {
0024 model = "MPC8323EMDS";
0025 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
0026 #address-cells = <1>;
0027 #size-cells = <1>;
0028
0029 aliases {
0030 ethernet0 = &enet0;
0031 ethernet1 = &enet1;
0032 serial0 = &serial0;
0033 serial1 = &serial1;
0034 pci0 = &pci0;
0035 };
0036
0037 cpus {
0038 #address-cells = <1>;
0039 #size-cells = <0>;
0040
0041 PowerPC,8323@0 {
0042 device_type = "cpu";
0043 reg = <0x0>;
0044 d-cache-line-size = <32>; // 32 bytes
0045 i-cache-line-size = <32>; // 32 bytes
0046 d-cache-size = <16384>; // L1, 16K
0047 i-cache-size = <16384>; // L1, 16K
0048 timebase-frequency = <0>;
0049 bus-frequency = <0>;
0050 clock-frequency = <0>;
0051 };
0052 };
0053
0054 memory {
0055 device_type = "memory";
0056 reg = <0x00000000 0x08000000>;
0057 };
0058
0059 bcsr@f8000000 {
0060 compatible = "fsl,mpc8323mds-bcsr";
0061 reg = <0xf8000000 0x8000>;
0062 };
0063
0064 soc8323@e0000000 {
0065 #address-cells = <1>;
0066 #size-cells = <1>;
0067 device_type = "soc";
0068 compatible = "simple-bus";
0069 ranges = <0x0 0xe0000000 0x00100000>;
0070 reg = <0xe0000000 0x00000200>;
0071 bus-frequency = <132000000>;
0072
0073 wdt@200 {
0074 device_type = "watchdog";
0075 compatible = "mpc83xx_wdt";
0076 reg = <0x200 0x100>;
0077 };
0078
0079 pmc: power@b00 {
0080 compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
0081 reg = <0xb00 0x100 0xa00 0x100>;
0082 interrupts = <80 0x8>;
0083 interrupt-parent = <&ipic>;
0084 };
0085
0086 i2c@3000 {
0087 #address-cells = <1>;
0088 #size-cells = <0>;
0089 cell-index = <0>;
0090 compatible = "fsl-i2c";
0091 reg = <0x3000 0x100>;
0092 interrupts = <14 0x8>;
0093 interrupt-parent = <&ipic>;
0094 dfsrr;
0095
0096 rtc@68 {
0097 compatible = "dallas,ds1374";
0098 reg = <0x68>;
0099 };
0100 };
0101
0102 serial0: serial@4500 {
0103 cell-index = <0>;
0104 device_type = "serial";
0105 compatible = "fsl,ns16550", "ns16550";
0106 reg = <0x4500 0x100>;
0107 clock-frequency = <0>;
0108 interrupts = <9 0x8>;
0109 interrupt-parent = <&ipic>;
0110 };
0111
0112 serial1: serial@4600 {
0113 cell-index = <1>;
0114 device_type = "serial";
0115 compatible = "fsl,ns16550", "ns16550";
0116 reg = <0x4600 0x100>;
0117 clock-frequency = <0>;
0118 interrupts = <10 0x8>;
0119 interrupt-parent = <&ipic>;
0120 };
0121
0122 dma@82a8 {
0123 #address-cells = <1>;
0124 #size-cells = <1>;
0125 compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
0126 reg = <0x82a8 4>;
0127 ranges = <0 0x8100 0x1a8>;
0128 interrupt-parent = <&ipic>;
0129 interrupts = <71 8>;
0130 cell-index = <0>;
0131 dma-channel@0 {
0132 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
0133 reg = <0 0x80>;
0134 cell-index = <0>;
0135 interrupt-parent = <&ipic>;
0136 interrupts = <71 8>;
0137 };
0138 dma-channel@80 {
0139 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
0140 reg = <0x80 0x80>;
0141 cell-index = <1>;
0142 interrupt-parent = <&ipic>;
0143 interrupts = <71 8>;
0144 };
0145 dma-channel@100 {
0146 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
0147 reg = <0x100 0x80>;
0148 cell-index = <2>;
0149 interrupt-parent = <&ipic>;
0150 interrupts = <71 8>;
0151 };
0152 dma-channel@180 {
0153 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
0154 reg = <0x180 0x28>;
0155 cell-index = <3>;
0156 interrupt-parent = <&ipic>;
0157 interrupts = <71 8>;
0158 };
0159 };
0160
0161 crypto@30000 {
0162 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
0163 reg = <0x30000 0x10000>;
0164 interrupts = <11 0x8>;
0165 interrupt-parent = <&ipic>;
0166 fsl,num-channels = <1>;
0167 fsl,channel-fifo-len = <24>;
0168 fsl,exec-units-mask = <0x4c>;
0169 fsl,descriptor-types-mask = <0x0122003f>;
0170 sleep = <&pmc 0x03000000>;
0171 };
0172
0173 ipic: pic@700 {
0174 interrupt-controller;
0175 #address-cells = <0>;
0176 #interrupt-cells = <2>;
0177 reg = <0x700 0x100>;
0178 device_type = "ipic";
0179 };
0180
0181 par_io@1400 {
0182 reg = <0x1400 0x100>;
0183 device_type = "par_io";
0184 num-ports = <7>;
0185
0186 pio3: ucc_pin@3 {
0187 pio-map = <
0188 /* port pin dir open_drain assignment has_irq */
0189 3 4 3 0 2 0 /* MDIO */
0190 3 5 1 0 2 0 /* MDC */
0191 0 13 2 0 1 0 /* RX_CLK (CLK9) */
0192 3 24 2 0 1 0 /* TX_CLK (CLK10) */
0193 1 0 1 0 1 0 /* TxD0 */
0194 1 1 1 0 1 0 /* TxD1 */
0195 1 2 1 0 1 0 /* TxD2 */
0196 1 3 1 0 1 0 /* TxD3 */
0197 1 4 2 0 1 0 /* RxD0 */
0198 1 5 2 0 1 0 /* RxD1 */
0199 1 6 2 0 1 0 /* RxD2 */
0200 1 7 2 0 1 0 /* RxD3 */
0201 1 8 2 0 1 0 /* RX_ER */
0202 1 9 1 0 1 0 /* TX_ER */
0203 1 10 2 0 1 0 /* RX_DV */
0204 1 11 2 0 1 0 /* COL */
0205 1 12 1 0 1 0 /* TX_EN */
0206 1 13 2 0 1 0>; /* CRS */
0207 };
0208 pio4: ucc_pin@4 {
0209 pio-map = <
0210 /* port pin dir open_drain assignment has_irq */
0211 3 31 2 0 1 0 /* RX_CLK (CLK7) */
0212 3 6 2 0 1 0 /* TX_CLK (CLK8) */
0213 1 18 1 0 1 0 /* TxD0 */
0214 1 19 1 0 1 0 /* TxD1 */
0215 1 20 1 0 1 0 /* TxD2 */
0216 1 21 1 0 1 0 /* TxD3 */
0217 1 22 2 0 1 0 /* RxD0 */
0218 1 23 2 0 1 0 /* RxD1 */
0219 1 24 2 0 1 0 /* RxD2 */
0220 1 25 2 0 1 0 /* RxD3 */
0221 1 26 2 0 1 0 /* RX_ER */
0222 1 27 1 0 1 0 /* TX_ER */
0223 1 28 2 0 1 0 /* RX_DV */
0224 1 29 2 0 1 0 /* COL */
0225 1 30 1 0 1 0 /* TX_EN */
0226 1 31 2 0 1 0>; /* CRS */
0227 };
0228 pio5: ucc_pin@5 {
0229 pio-map = <
0230 /*
0231 * open has
0232 * port pin dir drain sel irq
0233 */
0234 2 0 1 0 2 0 /* TxD5 */
0235 2 8 2 0 2 0 /* RxD5 */
0236
0237 2 29 2 0 0 0 /* CTS5 */
0238 2 31 1 0 2 0 /* RTS5 */
0239
0240 2 24 2 0 0 0 /* CD */
0241
0242 >;
0243 };
0244
0245 };
0246 };
0247
0248 qe@e0100000 {
0249 #address-cells = <1>;
0250 #size-cells = <1>;
0251 device_type = "qe";
0252 compatible = "fsl,qe";
0253 ranges = <0x0 0xe0100000 0x00100000>;
0254 reg = <0xe0100000 0x480>;
0255 brg-frequency = <0>;
0256 bus-frequency = <198000000>;
0257 fsl,qe-num-riscs = <1>;
0258 fsl,qe-num-snums = <28>;
0259
0260 muram@10000 {
0261 #address-cells = <1>;
0262 #size-cells = <1>;
0263 compatible = "fsl,qe-muram", "fsl,cpm-muram";
0264 ranges = <0x0 0x00010000 0x00004000>;
0265
0266 data-only@0 {
0267 compatible = "fsl,qe-muram-data",
0268 "fsl,cpm-muram-data";
0269 reg = <0x0 0x4000>;
0270 };
0271 };
0272
0273 spi@4c0 {
0274 cell-index = <0>;
0275 compatible = "fsl,spi";
0276 reg = <0x4c0 0x40>;
0277 interrupts = <2>;
0278 interrupt-parent = <&qeic>;
0279 mode = "cpu";
0280 };
0281
0282 spi@500 {
0283 cell-index = <1>;
0284 compatible = "fsl,spi";
0285 reg = <0x500 0x40>;
0286 interrupts = <1>;
0287 interrupt-parent = <&qeic>;
0288 mode = "cpu";
0289 };
0290
0291 usb@6c0 {
0292 compatible = "qe_udc";
0293 reg = <0x6c0 0x40 0x8b00 0x100>;
0294 interrupts = <11>;
0295 interrupt-parent = <&qeic>;
0296 mode = "slave";
0297 };
0298
0299 enet0: ucc@2200 {
0300 device_type = "network";
0301 compatible = "ucc_geth";
0302 cell-index = <3>;
0303 reg = <0x2200 0x200>;
0304 interrupts = <34>;
0305 interrupt-parent = <&qeic>;
0306 local-mac-address = [ 00 00 00 00 00 00 ];
0307 rx-clock-name = "clk9";
0308 tx-clock-name = "clk10";
0309 phy-handle = <&phy3>;
0310 pio-handle = <&pio3>;
0311 };
0312
0313 enet1: ucc@3200 {
0314 device_type = "network";
0315 compatible = "ucc_geth";
0316 cell-index = <4>;
0317 reg = <0x3200 0x200>;
0318 interrupts = <35>;
0319 interrupt-parent = <&qeic>;
0320 local-mac-address = [ 00 00 00 00 00 00 ];
0321 rx-clock-name = "clk7";
0322 tx-clock-name = "clk8";
0323 phy-handle = <&phy4>;
0324 pio-handle = <&pio4>;
0325 };
0326
0327 ucc@2400 {
0328 device_type = "serial";
0329 compatible = "ucc_uart";
0330 cell-index = <5>; /* The UCC number, 1-7*/
0331 port-number = <0>; /* Which ttyQEx device */
0332 soft-uart; /* We need Soft-UART */
0333 reg = <0x2400 0x200>;
0334 interrupts = <40>; /* From Table 18-12 */
0335 interrupt-parent = < &qeic >;
0336 /*
0337 * For Soft-UART, we need to set TX to 1X, which
0338 * means specifying separate clock sources.
0339 */
0340 rx-clock-name = "brg5";
0341 tx-clock-name = "brg6";
0342 pio-handle = < &pio5 >;
0343 };
0344
0345
0346 mdio@2320 {
0347 #address-cells = <1>;
0348 #size-cells = <0>;
0349 reg = <0x2320 0x18>;
0350 compatible = "fsl,ucc-mdio";
0351
0352 phy3: ethernet-phy@3 {
0353 interrupt-parent = <&ipic>;
0354 interrupts = <17 0x8>;
0355 reg = <0x3>;
0356 };
0357 phy4: ethernet-phy@4 {
0358 interrupt-parent = <&ipic>;
0359 interrupts = <18 0x8>;
0360 reg = <0x4>;
0361 };
0362 };
0363
0364 qeic: interrupt-controller@80 {
0365 interrupt-controller;
0366 compatible = "fsl,qe-ic";
0367 #address-cells = <0>;
0368 #interrupt-cells = <1>;
0369 reg = <0x80 0x80>;
0370 big-endian;
0371 interrupts = <32 0x8 33 0x8>; //high:32 low:33
0372 interrupt-parent = <&ipic>;
0373 };
0374 };
0375
0376 pci0: pci@e0008500 {
0377 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0378 interrupt-map = <
0379 /* IDSEL 0x11 AD17 */
0380 0x8800 0x0 0x0 0x1 &ipic 20 0x8
0381 0x8800 0x0 0x0 0x2 &ipic 21 0x8
0382 0x8800 0x0 0x0 0x3 &ipic 22 0x8
0383 0x8800 0x0 0x0 0x4 &ipic 23 0x8
0384
0385 /* IDSEL 0x12 AD18 */
0386 0x9000 0x0 0x0 0x1 &ipic 22 0x8
0387 0x9000 0x0 0x0 0x2 &ipic 23 0x8
0388 0x9000 0x0 0x0 0x3 &ipic 20 0x8
0389 0x9000 0x0 0x0 0x4 &ipic 21 0x8
0390
0391 /* IDSEL 0x13 AD19 */
0392 0x9800 0x0 0x0 0x1 &ipic 23 0x8
0393 0x9800 0x0 0x0 0x2 &ipic 20 0x8
0394 0x9800 0x0 0x0 0x3 &ipic 21 0x8
0395 0x9800 0x0 0x0 0x4 &ipic 22 0x8
0396
0397 /* IDSEL 0x15 AD21*/
0398 0xa800 0x0 0x0 0x1 &ipic 20 0x8
0399 0xa800 0x0 0x0 0x2 &ipic 21 0x8
0400 0xa800 0x0 0x0 0x3 &ipic 22 0x8
0401 0xa800 0x0 0x0 0x4 &ipic 23 0x8
0402
0403 /* IDSEL 0x16 AD22*/
0404 0xb000 0x0 0x0 0x1 &ipic 23 0x8
0405 0xb000 0x0 0x0 0x2 &ipic 20 0x8
0406 0xb000 0x0 0x0 0x3 &ipic 21 0x8
0407 0xb000 0x0 0x0 0x4 &ipic 22 0x8
0408
0409 /* IDSEL 0x17 AD23*/
0410 0xb800 0x0 0x0 0x1 &ipic 22 0x8
0411 0xb800 0x0 0x0 0x2 &ipic 23 0x8
0412 0xb800 0x0 0x0 0x3 &ipic 20 0x8
0413 0xb800 0x0 0x0 0x4 &ipic 21 0x8
0414
0415 /* IDSEL 0x18 AD24*/
0416 0xc000 0x0 0x0 0x1 &ipic 21 0x8
0417 0xc000 0x0 0x0 0x2 &ipic 22 0x8
0418 0xc000 0x0 0x0 0x3 &ipic 23 0x8
0419 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
0420 interrupt-parent = <&ipic>;
0421 interrupts = <66 0x8>;
0422 bus-range = <0x0 0x0>;
0423 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0424 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0425 0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
0426 clock-frequency = <0>;
0427 #interrupt-cells = <1>;
0428 #size-cells = <2>;
0429 #address-cells = <3>;
0430 reg = <0xe0008500 0x100 /* internal registers */
0431 0xe0008300 0x8>; /* config space access registers */
0432 compatible = "fsl,mpc8349-pci";
0433 device_type = "pci";
0434 sleep = <&pmc 0x00010000>;
0435 };
0436 };
