0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8315E RDB Device Tree Source
0004 *
0005 * Copyright 2007 Freescale Semiconductor Inc.
0006 */
0007
0008 /dts-v1/;
0009
0010 / {
0011 compatible = "fsl,mpc8315erdb";
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 aliases {
0016 ethernet0 = &enet0;
0017 ethernet1 = &enet1;
0018 serial0 = &serial0;
0019 serial1 = &serial1;
0020 pci0 = &pci0;
0021 pci1 = &pci1;
0022 pci2 = &pci2;
0023 };
0024
0025 cpus {
0026 #address-cells = <1>;
0027 #size-cells = <0>;
0028
0029 PowerPC,8315@0 {
0030 device_type = "cpu";
0031 reg = <0x0>;
0032 d-cache-line-size = <32>;
0033 i-cache-line-size = <32>;
0034 d-cache-size = <16384>;
0035 i-cache-size = <16384>;
0036 timebase-frequency = <0>; // from bootloader
0037 bus-frequency = <0>; // from bootloader
0038 clock-frequency = <0>; // from bootloader
0039 };
0040 };
0041
0042 memory {
0043 device_type = "memory";
0044 reg = <0x00000000 0x08000000>; // 128MB at 0
0045 };
0046
0047 localbus@e0005000 {
0048 #address-cells = <2>;
0049 #size-cells = <1>;
0050 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
0051 reg = <0xe0005000 0x1000>;
0052 interrupts = <77 0x8>;
0053 interrupt-parent = <&ipic>;
0054
0055 // CS0 and CS1 are swapped when
0056 // booting from nand, but the
0057 // addresses are the same.
0058 ranges = <0x0 0x0 0xfe000000 0x00800000
0059 0x1 0x0 0xe0600000 0x00002000
0060 0x2 0x0 0xf0000000 0x00020000
0061 0x3 0x0 0xfa000000 0x00008000>;
0062
0063 flash@0,0 {
0064 #address-cells = <1>;
0065 #size-cells = <1>;
0066 compatible = "cfi-flash";
0067 reg = <0x0 0x0 0x800000>;
0068 bank-width = <2>;
0069 device-width = <1>;
0070 };
0071
0072 nand@1,0 {
0073 #address-cells = <1>;
0074 #size-cells = <1>;
0075 compatible = "fsl,mpc8315-fcm-nand",
0076 "fsl,elbc-fcm-nand";
0077 reg = <0x1 0x0 0x2000>;
0078
0079 u-boot@0 {
0080 reg = <0x0 0x100000>;
0081 read-only;
0082 };
0083
0084 kernel@100000 {
0085 reg = <0x100000 0x300000>;
0086 };
0087 fs@400000 {
0088 reg = <0x400000 0x1c00000>;
0089 };
0090 };
0091 };
0092
0093 immr@e0000000 {
0094 #address-cells = <1>;
0095 #size-cells = <1>;
0096 device_type = "soc";
0097 compatible = "fsl,mpc8315-immr", "simple-bus";
0098 ranges = <0 0xe0000000 0x00100000>;
0099 reg = <0xe0000000 0x00000200>;
0100 bus-frequency = <0>;
0101
0102 wdt@200 {
0103 device_type = "watchdog";
0104 compatible = "mpc83xx_wdt";
0105 reg = <0x200 0x100>;
0106 };
0107
0108 i2c@3000 {
0109 #address-cells = <1>;
0110 #size-cells = <0>;
0111 cell-index = <0>;
0112 compatible = "fsl-i2c";
0113 reg = <0x3000 0x100>;
0114 interrupts = <14 0x8>;
0115 interrupt-parent = <&ipic>;
0116 dfsrr;
0117 rtc@68 {
0118 compatible = "dallas,ds1339";
0119 reg = <0x68>;
0120 };
0121
0122 mcu_pio: mcu@a {
0123 #gpio-cells = <2>;
0124 compatible = "fsl,mc9s08qg8-mpc8315erdb",
0125 "fsl,mcu-mpc8349emitx";
0126 reg = <0x0a>;
0127 gpio-controller;
0128 };
0129 };
0130
0131 spi@7000 {
0132 cell-index = <0>;
0133 compatible = "fsl,spi";
0134 reg = <0x7000 0x1000>;
0135 interrupts = <16 0x8>;
0136 interrupt-parent = <&ipic>;
0137 mode = "cpu";
0138 };
0139
0140 dma@82a8 {
0141 #address-cells = <1>;
0142 #size-cells = <1>;
0143 compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
0144 reg = <0x82a8 4>;
0145 ranges = <0 0x8100 0x1a8>;
0146 interrupt-parent = <&ipic>;
0147 interrupts = <71 8>;
0148 cell-index = <0>;
0149 dma-channel@0 {
0150 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
0151 reg = <0 0x80>;
0152 cell-index = <0>;
0153 interrupt-parent = <&ipic>;
0154 interrupts = <71 8>;
0155 };
0156 dma-channel@80 {
0157 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
0158 reg = <0x80 0x80>;
0159 cell-index = <1>;
0160 interrupt-parent = <&ipic>;
0161 interrupts = <71 8>;
0162 };
0163 dma-channel@100 {
0164 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
0165 reg = <0x100 0x80>;
0166 cell-index = <2>;
0167 interrupt-parent = <&ipic>;
0168 interrupts = <71 8>;
0169 };
0170 dma-channel@180 {
0171 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
0172 reg = <0x180 0x28>;
0173 cell-index = <3>;
0174 interrupt-parent = <&ipic>;
0175 interrupts = <71 8>;
0176 };
0177 };
0178
0179 usb@23000 {
0180 compatible = "fsl-usb2-dr";
0181 reg = <0x23000 0x1000>;
0182 #address-cells = <1>;
0183 #size-cells = <0>;
0184 interrupt-parent = <&ipic>;
0185 interrupts = <38 0x8>;
0186 phy_type = "utmi";
0187 };
0188
0189 enet0: ethernet@24000 {
0190 #address-cells = <1>;
0191 #size-cells = <1>;
0192 cell-index = <0>;
0193 device_type = "network";
0194 model = "eTSEC";
0195 compatible = "gianfar";
0196 reg = <0x24000 0x1000>;
0197 ranges = <0x0 0x24000 0x1000>;
0198 local-mac-address = [ 00 00 00 00 00 00 ];
0199 interrupts = <32 0x8 33 0x8 34 0x8>;
0200 interrupt-parent = <&ipic>;
0201 tbi-handle = <&tbi0>;
0202 phy-handle = < &phy0 >;
0203 fsl,magic-packet;
0204
0205 mdio@520 {
0206 #address-cells = <1>;
0207 #size-cells = <0>;
0208 compatible = "fsl,gianfar-mdio";
0209 reg = <0x520 0x20>;
0210
0211 phy0: ethernet-phy@0 {
0212 interrupt-parent = <&ipic>;
0213 interrupts = <20 0x8>;
0214 reg = <0x0>;
0215 };
0216
0217 phy1: ethernet-phy@1 {
0218 interrupt-parent = <&ipic>;
0219 interrupts = <19 0x8>;
0220 reg = <0x1>;
0221 };
0222
0223 tbi0: tbi-phy@11 {
0224 reg = <0x11>;
0225 device_type = "tbi-phy";
0226 };
0227 };
0228 };
0229
0230 enet1: ethernet@25000 {
0231 #address-cells = <1>;
0232 #size-cells = <1>;
0233 cell-index = <1>;
0234 device_type = "network";
0235 model = "eTSEC";
0236 compatible = "gianfar";
0237 reg = <0x25000 0x1000>;
0238 ranges = <0x0 0x25000 0x1000>;
0239 local-mac-address = [ 00 00 00 00 00 00 ];
0240 interrupts = <35 0x8 36 0x8 37 0x8>;
0241 interrupt-parent = <&ipic>;
0242 tbi-handle = <&tbi1>;
0243 phy-handle = < &phy1 >;
0244 fsl,magic-packet;
0245
0246 mdio@520 {
0247 #address-cells = <1>;
0248 #size-cells = <0>;
0249 compatible = "fsl,gianfar-tbi";
0250 reg = <0x520 0x20>;
0251
0252 tbi1: tbi-phy@11 {
0253 reg = <0x11>;
0254 device_type = "tbi-phy";
0255 };
0256 };
0257 };
0258
0259 serial0: serial@4500 {
0260 cell-index = <0>;
0261 device_type = "serial";
0262 compatible = "fsl,ns16550", "ns16550";
0263 reg = <0x4500 0x100>;
0264 clock-frequency = <133333333>;
0265 interrupts = <9 0x8>;
0266 interrupt-parent = <&ipic>;
0267 };
0268
0269 serial1: serial@4600 {
0270 cell-index = <1>;
0271 device_type = "serial";
0272 compatible = "fsl,ns16550", "ns16550";
0273 reg = <0x4600 0x100>;
0274 clock-frequency = <133333333>;
0275 interrupts = <10 0x8>;
0276 interrupt-parent = <&ipic>;
0277 };
0278
0279 crypto@30000 {
0280 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
0281 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
0282 "fsl,sec2.0";
0283 reg = <0x30000 0x10000>;
0284 interrupts = <11 0x8>;
0285 interrupt-parent = <&ipic>;
0286 fsl,num-channels = <4>;
0287 fsl,channel-fifo-len = <24>;
0288 fsl,exec-units-mask = <0x97c>;
0289 fsl,descriptor-types-mask = <0x3a30abf>;
0290 };
0291
0292 sata@18000 {
0293 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
0294 reg = <0x18000 0x1000>;
0295 cell-index = <1>;
0296 interrupts = <44 0x8>;
0297 interrupt-parent = <&ipic>;
0298 };
0299
0300 sata@19000 {
0301 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
0302 reg = <0x19000 0x1000>;
0303 cell-index = <2>;
0304 interrupts = <45 0x8>;
0305 interrupt-parent = <&ipic>;
0306 };
0307
0308 gtm1: timer@500 {
0309 compatible = "fsl,mpc8315-gtm", "fsl,gtm";
0310 reg = <0x500 0x100>;
0311 interrupts = <90 8 78 8 84 8 72 8>;
0312 interrupt-parent = <&ipic>;
0313 clock-frequency = <133333333>;
0314 };
0315
0316 timer@600 {
0317 compatible = "fsl,mpc8315-gtm", "fsl,gtm";
0318 reg = <0x600 0x100>;
0319 interrupts = <91 8 79 8 85 8 73 8>;
0320 interrupt-parent = <&ipic>;
0321 clock-frequency = <133333333>;
0322 };
0323
0324 /* IPIC
0325 * interrupts cell = <intr #, sense>
0326 * sense values match linux IORESOURCE_IRQ_* defines:
0327 * sense == 8: Level, low assertion
0328 * sense == 2: Edge, high-to-low change
0329 */
0330 ipic: interrupt-controller@700 {
0331 interrupt-controller;
0332 #address-cells = <0>;
0333 #interrupt-cells = <2>;
0334 reg = <0x700 0x100>;
0335 device_type = "ipic";
0336 };
0337
0338 ipic-msi@7c0 {
0339 compatible = "fsl,ipic-msi";
0340 reg = <0x7c0 0x40>;
0341 msi-available-ranges = <0 0x100>;
0342 interrupts = <0x43 0x8
0343 0x4 0x8
0344 0x51 0x8
0345 0x52 0x8
0346 0x56 0x8
0347 0x57 0x8
0348 0x58 0x8
0349 0x59 0x8>;
0350 interrupt-parent = < &ipic >;
0351 };
0352
0353 pmc: power@b00 {
0354 compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
0355 "fsl,mpc8349-pmc";
0356 reg = <0xb00 0x100 0xa00 0x100>;
0357 interrupts = <80 8>;
0358 interrupt-parent = <&ipic>;
0359 fsl,mpc8313-wakeup-timer = <>m1>;
0360 };
0361 };
0362
0363 pci0: pci@e0008500 {
0364 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0365 interrupt-map = <
0366 /* IDSEL 0x0E -mini PCI */
0367 0x7000 0x0 0x0 0x1 &ipic 18 0x8
0368 0x7000 0x0 0x0 0x2 &ipic 18 0x8
0369 0x7000 0x0 0x0 0x3 &ipic 18 0x8
0370 0x7000 0x0 0x0 0x4 &ipic 18 0x8
0371
0372 /* IDSEL 0x0F -mini PCI */
0373 0x7800 0x0 0x0 0x1 &ipic 17 0x8
0374 0x7800 0x0 0x0 0x2 &ipic 17 0x8
0375 0x7800 0x0 0x0 0x3 &ipic 17 0x8
0376 0x7800 0x0 0x0 0x4 &ipic 17 0x8
0377
0378 /* IDSEL 0x10 - PCI slot */
0379 0x8000 0x0 0x0 0x1 &ipic 48 0x8
0380 0x8000 0x0 0x0 0x2 &ipic 17 0x8
0381 0x8000 0x0 0x0 0x3 &ipic 48 0x8
0382 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
0383 interrupt-parent = <&ipic>;
0384 interrupts = <66 0x8>;
0385 bus-range = <0x0 0x0>;
0386 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
0387 0x42000000 0 0x80000000 0x80000000 0 0x10000000
0388 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
0389 clock-frequency = <66666666>;
0390 #interrupt-cells = <1>;
0391 #size-cells = <2>;
0392 #address-cells = <3>;
0393 reg = <0xe0008500 0x100 /* internal registers */
0394 0xe0008300 0x8>; /* config space access registers */
0395 compatible = "fsl,mpc8349-pci";
0396 device_type = "pci";
0397 };
0398
0399 pci1: pcie@e0009000 {
0400 #address-cells = <3>;
0401 #size-cells = <2>;
0402 #interrupt-cells = <1>;
0403 device_type = "pci";
0404 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
0405 reg = <0xe0009000 0x00001000>;
0406 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0407 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
0408 bus-range = <0 255>;
0409 interrupt-map-mask = <0xf800 0 0 7>;
0410 interrupt-map = <0 0 0 1 &ipic 1 8
0411 0 0 0 2 &ipic 1 8
0412 0 0 0 3 &ipic 1 8
0413 0 0 0 4 &ipic 1 8>;
0414 clock-frequency = <0>;
0415
0416 pcie@0 {
0417 #address-cells = <3>;
0418 #size-cells = <2>;
0419 device_type = "pci";
0420 reg = <0 0 0 0 0>;
0421 ranges = <0x02000000 0 0xa0000000
0422 0x02000000 0 0xa0000000
0423 0 0x10000000
0424 0x01000000 0 0x00000000
0425 0x01000000 0 0x00000000
0426 0 0x00800000>;
0427 };
0428 };
0429
0430 pci2: pcie@e000a000 {
0431 #address-cells = <3>;
0432 #size-cells = <2>;
0433 #interrupt-cells = <1>;
0434 device_type = "pci";
0435 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
0436 reg = <0xe000a000 0x00001000>;
0437 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
0438 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
0439 bus-range = <0 255>;
0440 interrupt-map-mask = <0xf800 0 0 7>;
0441 interrupt-map = <0 0 0 1 &ipic 2 8
0442 0 0 0 2 &ipic 2 8
0443 0 0 0 3 &ipic 2 8
0444 0 0 0 4 &ipic 2 8>;
0445 clock-frequency = <0>;
0446
0447 pcie@0 {
0448 #address-cells = <3>;
0449 #size-cells = <2>;
0450 device_type = "pci";
0451 reg = <0 0 0 0 0>;
0452 ranges = <0x02000000 0 0xc0000000
0453 0x02000000 0 0xc0000000
0454 0 0x10000000
0455 0x01000000 0 0x00000000
0456 0x01000000 0 0x00000000
0457 0 0x00800000>;
0458 };
0459 };
0460
0461 leds {
0462 compatible = "gpio-leds";
0463
0464 pwr {
0465 gpios = <&mcu_pio 0 0>;
0466 default-state = "on";
0467 };
0468
0469 hdd {
0470 gpios = <&mcu_pio 1 0>;
0471 linux,default-trigger = "disk-activity";
0472 };
0473 };
0474 };
