0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8308RDB Device Tree Source
0004 *
0005 * Copyright 2009 Freescale Semiconductor Inc.
0006 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
0007 */
0008
0009 /dts-v1/;
0010
0011 / {
0012 compatible = "fsl,mpc8308rdb";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 aliases {
0017 ethernet0 = &enet0;
0018 ethernet1 = &enet1;
0019 serial0 = &serial0;
0020 serial1 = &serial1;
0021 pci0 = &pci0;
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 PowerPC,8308@0 {
0029 device_type = "cpu";
0030 reg = <0x0>;
0031 d-cache-line-size = <32>;
0032 i-cache-line-size = <32>;
0033 d-cache-size = <16384>;
0034 i-cache-size = <16384>;
0035 timebase-frequency = <0>; // from bootloader
0036 bus-frequency = <0>; // from bootloader
0037 clock-frequency = <0>; // from bootloader
0038 };
0039 };
0040
0041 memory {
0042 device_type = "memory";
0043 reg = <0x00000000 0x08000000>; // 128MB at 0
0044 };
0045
0046 localbus@e0005000 {
0047 #address-cells = <2>;
0048 #size-cells = <1>;
0049 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
0050 reg = <0xe0005000 0x1000>;
0051 interrupts = <77 0x8>;
0052 interrupt-parent = <&ipic>;
0053
0054 // CS0 and CS1 are swapped when
0055 // booting from nand, but the
0056 // addresses are the same.
0057 ranges = <0x0 0x0 0xfe000000 0x00800000
0058 0x1 0x0 0xe0600000 0x00002000
0059 0x2 0x0 0xf0000000 0x00020000
0060 0x3 0x0 0xfa000000 0x00008000>;
0061
0062 flash@0,0 {
0063 #address-cells = <1>;
0064 #size-cells = <1>;
0065 compatible = "cfi-flash";
0066 reg = <0x0 0x0 0x800000>;
0067 bank-width = <2>;
0068 device-width = <1>;
0069
0070 u-boot@0 {
0071 reg = <0x0 0x60000>;
0072 read-only;
0073 };
0074 env@60000 {
0075 reg = <0x60000 0x10000>;
0076 };
0077 env1@70000 {
0078 reg = <0x70000 0x10000>;
0079 };
0080 kernel@80000 {
0081 reg = <0x80000 0x200000>;
0082 };
0083 dtb@280000 {
0084 reg = <0x280000 0x10000>;
0085 };
0086 ramdisk@290000 {
0087 reg = <0x290000 0x570000>;
0088 };
0089 };
0090
0091 nand@1,0 {
0092 #address-cells = <1>;
0093 #size-cells = <1>;
0094 compatible = "fsl,mpc8315-fcm-nand",
0095 "fsl,elbc-fcm-nand";
0096 reg = <0x1 0x0 0x2000>;
0097
0098 jffs2@0 {
0099 reg = <0x0 0x2000000>;
0100 };
0101 };
0102 };
0103
0104 immr@e0000000 {
0105 #address-cells = <1>;
0106 #size-cells = <1>;
0107 device_type = "soc";
0108 compatible = "fsl,mpc8308-immr", "simple-bus";
0109 ranges = <0 0xe0000000 0x00100000>;
0110 reg = <0xe0000000 0x00000200>;
0111 bus-frequency = <0>;
0112
0113 i2c@3000 {
0114 #address-cells = <1>;
0115 #size-cells = <0>;
0116 cell-index = <0>;
0117 compatible = "fsl-i2c";
0118 reg = <0x3000 0x100>;
0119 interrupts = <14 0x8>;
0120 interrupt-parent = <&ipic>;
0121 dfsrr;
0122 rtc@68 {
0123 compatible = "dallas,ds1339";
0124 reg = <0x68>;
0125 };
0126 };
0127
0128 usb@23000 {
0129 compatible = "fsl-usb2-dr";
0130 reg = <0x23000 0x1000>;
0131 #address-cells = <1>;
0132 #size-cells = <0>;
0133 interrupt-parent = <&ipic>;
0134 interrupts = <38 0x8>;
0135 dr_mode = "peripheral";
0136 phy_type = "ulpi";
0137 };
0138
0139 enet0: ethernet@24000 {
0140 #address-cells = <1>;
0141 #size-cells = <1>;
0142 ranges = <0x0 0x24000 0x1000>;
0143
0144 cell-index = <0>;
0145 device_type = "network";
0146 model = "eTSEC";
0147 compatible = "gianfar";
0148 reg = <0x24000 0x1000>;
0149 local-mac-address = [ 00 00 00 00 00 00 ];
0150 interrupts = <32 0x8 33 0x8 34 0x8>;
0151 interrupt-parent = <&ipic>;
0152 tbi-handle = < &tbi0 >;
0153 phy-handle = < &phy2 >;
0154 fsl,magic-packet;
0155
0156 mdio@520 {
0157 #address-cells = <1>;
0158 #size-cells = <0>;
0159 compatible = "fsl,gianfar-mdio";
0160 reg = <0x520 0x20>;
0161 phy2: ethernet-phy@2 {
0162 interrupt-parent = <&ipic>;
0163 interrupts = <17 0x8>;
0164 reg = <0x2>;
0165 };
0166 tbi0: tbi-phy@11 {
0167 reg = <0x11>;
0168 device_type = "tbi-phy";
0169 };
0170 };
0171 };
0172
0173 enet1: ethernet@25000 {
0174 #address-cells = <1>;
0175 #size-cells = <1>;
0176 cell-index = <1>;
0177 device_type = "network";
0178 model = "eTSEC";
0179 compatible = "gianfar";
0180 reg = <0x25000 0x1000>;
0181 ranges = <0x0 0x25000 0x1000>;
0182 local-mac-address = [ 00 00 00 00 00 00 ];
0183 interrupts = <35 0x8 36 0x8 37 0x8>;
0184 interrupt-parent = <&ipic>;
0185 tbi-handle = < &tbi1 >;
0186 /* Vitesse 7385 isn't on the MDIO bus */
0187 fixed-link = <1 1 1000 0 0>;
0188 fsl,magic-packet;
0189
0190 mdio@520 {
0191 #address-cells = <1>;
0192 #size-cells = <0>;
0193 compatible = "fsl,gianfar-tbi";
0194 reg = <0x520 0x20>;
0195
0196 tbi1: tbi-phy@11 {
0197 reg = <0x11>;
0198 device_type = "tbi-phy";
0199 };
0200 };
0201 };
0202
0203 serial0: serial@4500 {
0204 cell-index = <0>;
0205 device_type = "serial";
0206 compatible = "fsl,ns16550", "ns16550";
0207 reg = <0x4500 0x100>;
0208 clock-frequency = <133333333>;
0209 interrupts = <9 0x8>;
0210 interrupt-parent = <&ipic>;
0211 };
0212
0213 serial1: serial@4600 {
0214 cell-index = <1>;
0215 device_type = "serial";
0216 compatible = "fsl,ns16550", "ns16550";
0217 reg = <0x4600 0x100>;
0218 clock-frequency = <133333333>;
0219 interrupts = <10 0x8>;
0220 interrupt-parent = <&ipic>;
0221 };
0222
0223 gpio@c00 {
0224 #gpio-cells = <2>;
0225 device_type = "gpio";
0226 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
0227 reg = <0xc00 0x18>;
0228 interrupts = <74 0x8>;
0229 interrupt-parent = <&ipic>;
0230 gpio-controller;
0231 };
0232
0233 /* IPIC
0234 * interrupts cell = <intr #, sense>
0235 * sense values match linux IORESOURCE_IRQ_* defines:
0236 * sense == 8: Level, low assertion
0237 * sense == 2: Edge, high-to-low change
0238 */
0239 ipic: interrupt-controller@700 {
0240 compatible = "fsl,ipic";
0241 interrupt-controller;
0242 #address-cells = <0>;
0243 #interrupt-cells = <2>;
0244 reg = <0x700 0x100>;
0245 device_type = "ipic";
0246 };
0247
0248 ipic-msi@7c0 {
0249 compatible = "fsl,ipic-msi";
0250 reg = <0x7c0 0x40>;
0251 msi-available-ranges = <0x0 0x100>;
0252 interrupts = < 0x43 0x8
0253 0x4 0x8
0254 0x51 0x8
0255 0x52 0x8
0256 0x56 0x8
0257 0x57 0x8
0258 0x58 0x8
0259 0x59 0x8 >;
0260 interrupt-parent = < &ipic >;
0261 };
0262
0263 dma@2c000 {
0264 compatible = "fsl,mpc8308-dma";
0265 reg = <0x2c000 0x1800>;
0266 interrupts = <3 0x8
0267 94 0x8>;
0268 interrupt-parent = < &ipic >;
0269 };
0270
0271 };
0272
0273 pci0: pcie@e0009000 {
0274 #address-cells = <3>;
0275 #size-cells = <2>;
0276 #interrupt-cells = <1>;
0277 device_type = "pci";
0278 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
0279 reg = <0xe0009000 0x00001000
0280 0xb0000000 0x01000000>;
0281 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0282 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
0283 bus-range = <0 0>;
0284 interrupt-map-mask = <0xf800 0 0 7>;
0285 interrupt-map = <0 0 0 1 &ipic 1 8
0286 0 0 0 2 &ipic 1 8
0287 0 0 0 3 &ipic 1 8
0288 0 0 0 4 &ipic 1 8>;
0289 interrupts = <0x1 0x8>;
0290 interrupt-parent = <&ipic>;
0291 clock-frequency = <0>;
0292
0293 pcie@0 {
0294 #address-cells = <3>;
0295 #size-cells = <2>;
0296 device_type = "pci";
0297 reg = <0 0 0 0 0>;
0298 ranges = <0x02000000 0 0xa0000000
0299 0x02000000 0 0xa0000000
0300 0 0x10000000
0301 0x01000000 0 0x00000000
0302 0x01000000 0 0x00000000
0303 0 0x00800000>;
0304 };
0305 };
0306 };
