0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * STx/Freescale ADS5125 MPC5125 silicon
0004 *
0005 * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
0006 *
0007 * Reworked by Matteo Facchinetti (engineering@sirius-es.it)
0008 * Copyright (C) 2013 Sirius Electronic Systems
0009 */
0010
0011 #include <dt-bindings/clock/mpc512x-clock.h>
0012
0013 /dts-v1/;
0014
0015 / {
0016 model = "mpc5125twr"; // In BSP "mpc5125ads"
0017 compatible = "fsl,mpc5125ads", "fsl,mpc5125";
0018 #address-cells = <1>;
0019 #size-cells = <1>;
0020 interrupt-parent = <&ipic>;
0021
0022 aliases {
0023 gpio0 = &gpio0;
0024 gpio1 = &gpio1;
0025 ethernet0 = ð0;
0026 };
0027
0028 cpus {
0029 #address-cells = <1>;
0030 #size-cells = <0>;
0031
0032 PowerPC,5125@0 {
0033 device_type = "cpu";
0034 reg = <0>;
0035 d-cache-line-size = <0x20>; // 32 bytes
0036 i-cache-line-size = <0x20>; // 32 bytes
0037 d-cache-size = <0x8000>; // L1, 32K
0038 i-cache-size = <0x8000>; // L1, 32K
0039 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
0040 bus-frequency = <198000000>; // 198 MHz csb bus
0041 clock-frequency = <396000000>; // 396 MHz ppc core
0042 };
0043 };
0044
0045 memory {
0046 device_type = "memory";
0047 reg = <0x00000000 0x10000000>; // 256MB at 0
0048 };
0049
0050 sram@30000000 {
0051 compatible = "fsl,mpc5121-sram";
0052 reg = <0x30000000 0x08000>; // 32K at 0x30000000
0053 };
0054
0055 clocks {
0056 #address-cells = <1>;
0057 #size-cells = <0>;
0058
0059 osc: osc {
0060 compatible = "fixed-clock";
0061 #clock-cells = <0>;
0062 clock-frequency = <33000000>;
0063 };
0064 };
0065
0066 soc@80000000 {
0067 compatible = "fsl,mpc5121-immr";
0068 #address-cells = <1>;
0069 #size-cells = <1>;
0070 ranges = <0x0 0x80000000 0x400000>;
0071 reg = <0x80000000 0x400000>;
0072 bus-frequency = <66000000>; // 66 MHz ips bus
0073
0074 // IPIC
0075 // interrupts cell = <intr #, sense>
0076 // sense values match linux IORESOURCE_IRQ_* defines:
0077 // sense == 8: Level, low assertion
0078 // sense == 2: Edge, high-to-low change
0079 //
0080 ipic: interrupt-controller@c00 {
0081 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
0082 interrupt-controller;
0083 #address-cells = <0>;
0084 #interrupt-cells = <2>;
0085 reg = <0xc00 0x100>;
0086 };
0087
0088 rtc@a00 { // Real time clock
0089 compatible = "fsl,mpc5121-rtc";
0090 reg = <0xa00 0x100>;
0091 interrupts = <79 0x8 80 0x8>;
0092 };
0093
0094 reset@e00 { // Reset module
0095 compatible = "fsl,mpc5125-reset";
0096 reg = <0xe00 0x100>;
0097 };
0098
0099 clks: clock@f00 { // Clock control
0100 compatible = "fsl,mpc5121-clock";
0101 reg = <0xf00 0x100>;
0102 #clock-cells = <1>;
0103 clocks = <&osc>;
0104 clock-names = "osc";
0105 };
0106
0107 pmc@1000{ // Power Management Controller
0108 compatible = "fsl,mpc5121-pmc";
0109 reg = <0x1000 0x100>;
0110 interrupts = <83 0x2>;
0111 };
0112
0113 gpio0: gpio@1100 {
0114 compatible = "fsl,mpc5125-gpio";
0115 reg = <0x1100 0x080>;
0116 interrupts = <78 0x8>;
0117 };
0118
0119 gpio1: gpio@1180 {
0120 compatible = "fsl,mpc5125-gpio";
0121 reg = <0x1180 0x080>;
0122 interrupts = <86 0x8>;
0123 };
0124
0125 can@1300 { // CAN rev.2
0126 compatible = "fsl,mpc5121-mscan";
0127 interrupts = <12 0x8>;
0128 reg = <0x1300 0x80>;
0129 clocks = <&clks MPC512x_CLK_BDLC>,
0130 <&clks MPC512x_CLK_IPS>,
0131 <&clks MPC512x_CLK_SYS>,
0132 <&clks MPC512x_CLK_REF>,
0133 <&clks MPC512x_CLK_MSCAN0_MCLK>;
0134 clock-names = "ipg", "ips", "sys", "ref", "mclk";
0135 };
0136
0137 can@1380 {
0138 compatible = "fsl,mpc5121-mscan";
0139 interrupts = <13 0x8>;
0140 reg = <0x1380 0x80>;
0141 clocks = <&clks MPC512x_CLK_BDLC>,
0142 <&clks MPC512x_CLK_IPS>,
0143 <&clks MPC512x_CLK_SYS>,
0144 <&clks MPC512x_CLK_REF>,
0145 <&clks MPC512x_CLK_MSCAN1_MCLK>;
0146 clock-names = "ipg", "ips", "sys", "ref", "mclk";
0147 };
0148
0149 sdhc@1500 {
0150 compatible = "fsl,mpc5121-sdhc";
0151 interrupts = <8 0x8>;
0152 reg = <0x1500 0x100>;
0153 clocks = <&clks MPC512x_CLK_IPS>,
0154 <&clks MPC512x_CLK_SDHC>;
0155 clock-names = "ipg", "per";
0156 };
0157
0158 i2c@1700 {
0159 #address-cells = <1>;
0160 #size-cells = <0>;
0161 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
0162 reg = <0x1700 0x20>;
0163 interrupts = <0x9 0x8>;
0164 clocks = <&clks MPC512x_CLK_I2C>;
0165 clock-names = "ipg";
0166 };
0167
0168 i2c@1720 {
0169 #address-cells = <1>;
0170 #size-cells = <0>;
0171 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
0172 reg = <0x1720 0x20>;
0173 interrupts = <0xa 0x8>;
0174 clocks = <&clks MPC512x_CLK_I2C>;
0175 clock-names = "ipg";
0176 };
0177
0178 i2c@1740 {
0179 #address-cells = <1>;
0180 #size-cells = <0>;
0181 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
0182 reg = <0x1740 0x20>;
0183 interrupts = <0xb 0x8>;
0184 clocks = <&clks MPC512x_CLK_I2C>;
0185 clock-names = "ipg";
0186 };
0187
0188 i2ccontrol@1760 {
0189 compatible = "fsl,mpc5121-i2c-ctrl";
0190 reg = <0x1760 0x8>;
0191 };
0192
0193 diu@2100 {
0194 compatible = "fsl,mpc5121-diu";
0195 reg = <0x2100 0x100>;
0196 interrupts = <64 0x8>;
0197 clocks = <&clks MPC512x_CLK_DIU>;
0198 clock-names = "ipg";
0199 };
0200
0201 mdio@2800 {
0202 compatible = "fsl,mpc5121-fec-mdio";
0203 reg = <0x2800 0x800>;
0204 #address-cells = <1>;
0205 #size-cells = <0>;
0206 phy0: ethernet-phy@0 {
0207 reg = <1>;
0208 };
0209 };
0210
0211 eth0: ethernet@2800 {
0212 compatible = "fsl,mpc5125-fec";
0213 reg = <0x2800 0x800>;
0214 local-mac-address = [ 00 00 00 00 00 00 ];
0215 interrupts = <4 0x8>;
0216 phy-handle = < &phy0 >;
0217 phy-connection-type = "rmii";
0218 clocks = <&clks MPC512x_CLK_FEC>;
0219 clock-names = "per";
0220 };
0221
0222 // IO control
0223 ioctl@a000 {
0224 compatible = "fsl,mpc5125-ioctl";
0225 reg = <0xA000 0x1000>;
0226 };
0227
0228 // disable USB1 port
0229 // TODO:
0230 // correct pinmux config and fix USB3320 ulpi dependency
0231 // before re-enabling it
0232 usb@3000 {
0233 compatible = "fsl,mpc5121-usb2-dr";
0234 reg = <0x3000 0x400>;
0235 #address-cells = <1>;
0236 #size-cells = <0>;
0237 interrupts = <43 0x8>;
0238 dr_mode = "host";
0239 phy_type = "ulpi";
0240 clocks = <&clks MPC512x_CLK_USB1>;
0241 clock-names = "ipg";
0242 status = "disabled";
0243 };
0244
0245 sclpc@10100 {
0246 compatible = "fsl,mpc512x-lpbfifo";
0247 reg = <0x10100 0x50>;
0248 interrupts = <7 0x8>;
0249 dmas = <&dma0 26>;
0250 dma-names = "rx-tx";
0251 };
0252
0253 // 5125 PSCs are not 52xx or 5121 PSC compatible
0254 // PSC1 uart0 aka ttyPSC0
0255 serial@11100 {
0256 compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
0257 reg = <0x11100 0x100>;
0258 interrupts = <40 0x8>;
0259 fsl,rx-fifo-size = <16>;
0260 fsl,tx-fifo-size = <16>;
0261 clocks = <&clks MPC512x_CLK_PSC1>,
0262 <&clks MPC512x_CLK_PSC1_MCLK>;
0263 clock-names = "ipg", "mclk";
0264 };
0265
0266 // PSC9 uart1 aka ttyPSC1
0267 serial@11900 {
0268 compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
0269 reg = <0x11900 0x100>;
0270 interrupts = <40 0x8>;
0271 fsl,rx-fifo-size = <16>;
0272 fsl,tx-fifo-size = <16>;
0273 clocks = <&clks MPC512x_CLK_PSC9>,
0274 <&clks MPC512x_CLK_PSC9_MCLK>;
0275 clock-names = "ipg", "mclk";
0276 };
0277
0278 pscfifo@11f00 {
0279 compatible = "fsl,mpc5121-psc-fifo";
0280 reg = <0x11f00 0x100>;
0281 interrupts = <40 0x8>;
0282 clocks = <&clks MPC512x_CLK_PSC_FIFO>;
0283 clock-names = "ipg";
0284 };
0285
0286 dma0: dma@14000 {
0287 compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"
0288 reg = <0x14000 0x1800>;
0289 interrupts = <65 0x8>;
0290 #dma-cells = <1>;
0291 };
0292 };
0293 };
