0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * base MPC5121 Device Tree Source
0004 *
0005 * Copyright 2007-2008 Freescale Semiconductor Inc.
0006 */
0007
0008 #include <dt-bindings/clock/mpc512x-clock.h>
0009
0010 /dts-v1/;
0011
0012 / {
0013 model = "mpc5121";
0014 compatible = "fsl,mpc5121";
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017 interrupt-parent = <&ipic>;
0018
0019 aliases {
0020 ethernet0 = ð0;
0021 pci = &pci;
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 PowerPC,5121@0 {
0029 device_type = "cpu";
0030 reg = <0>;
0031 d-cache-line-size = <0x20>; /* 32 bytes */
0032 i-cache-line-size = <0x20>; /* 32 bytes */
0033 d-cache-size = <0x8000>; /* L1, 32K */
0034 i-cache-size = <0x8000>; /* L1, 32K */
0035 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
0036 bus-frequency = <198000000>; /* 198 MHz csb bus */
0037 clock-frequency = <396000000>; /* 396 MHz ppc core */
0038 };
0039 };
0040
0041 memory {
0042 device_type = "memory";
0043 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
0044 };
0045
0046 mbx@20000000 {
0047 compatible = "fsl,mpc5121-mbx";
0048 reg = <0x20000000 0x4000>;
0049 interrupts = <66 0x8>;
0050 clocks = <&clks MPC512x_CLK_MBX_BUS>,
0051 <&clks MPC512x_CLK_MBX_3D>,
0052 <&clks MPC512x_CLK_MBX>;
0053 clock-names = "mbx-bus", "mbx-3d", "mbx";
0054 };
0055
0056 sram@30000000 {
0057 compatible = "fsl,mpc5121-sram";
0058 reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */
0059 };
0060
0061 nfc@40000000 {
0062 compatible = "fsl,mpc5121-nfc";
0063 reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */
0064 interrupts = <6 8>;
0065 #address-cells = <1>;
0066 #size-cells = <1>;
0067 clocks = <&clks MPC512x_CLK_NFC>;
0068 clock-names = "ipg";
0069 };
0070
0071 localbus@80000020 {
0072 compatible = "fsl,mpc5121-localbus";
0073 #address-cells = <2>;
0074 #size-cells = <1>;
0075 reg = <0x80000020 0x40>;
0076 ranges = <0x0 0x0 0xfc000000 0x04000000>;
0077 };
0078
0079 clocks {
0080 #address-cells = <1>;
0081 #size-cells = <0>;
0082
0083 osc: osc {
0084 compatible = "fixed-clock";
0085 #clock-cells = <0>;
0086 clock-frequency = <33000000>;
0087 };
0088 };
0089
0090 soc@80000000 {
0091 compatible = "fsl,mpc5121-immr";
0092 #address-cells = <1>;
0093 #size-cells = <1>;
0094 ranges = <0x0 0x80000000 0x400000>;
0095 reg = <0x80000000 0x400000>;
0096 bus-frequency = <66000000>; /* 66 MHz ips bus */
0097
0098
0099 /*
0100 * IPIC
0101 * interrupts cell = <intr #, sense>
0102 * sense values match linux IORESOURCE_IRQ_* defines:
0103 * sense == 8: Level, low assertion
0104 * sense == 2: Edge, high-to-low change
0105 */
0106 ipic: interrupt-controller@c00 {
0107 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
0108 interrupt-controller;
0109 #address-cells = <0>;
0110 #interrupt-cells = <2>;
0111 reg = <0xc00 0x100>;
0112 };
0113
0114 /* Watchdog timer */
0115 wdt@900 {
0116 compatible = "fsl,mpc5121-wdt";
0117 reg = <0x900 0x100>;
0118 };
0119
0120 /* Real time clock */
0121 rtc@a00 {
0122 compatible = "fsl,mpc5121-rtc";
0123 reg = <0xa00 0x100>;
0124 interrupts = <79 0x8 80 0x8>;
0125 };
0126
0127 /* Reset module */
0128 reset@e00 {
0129 compatible = "fsl,mpc5121-reset";
0130 reg = <0xe00 0x100>;
0131 };
0132
0133 /* Clock control */
0134 clks: clock@f00 {
0135 compatible = "fsl,mpc5121-clock";
0136 reg = <0xf00 0x100>;
0137 #clock-cells = <1>;
0138 clocks = <&osc>;
0139 clock-names = "osc";
0140 };
0141
0142 /* Power Management Controller */
0143 pmc@1000{
0144 compatible = "fsl,mpc5121-pmc";
0145 reg = <0x1000 0x100>;
0146 interrupts = <83 0x8>;
0147 };
0148
0149 gpio@1100 {
0150 compatible = "fsl,mpc5121-gpio";
0151 reg = <0x1100 0x100>;
0152 interrupts = <78 0x8>;
0153 };
0154
0155 can@1300 {
0156 compatible = "fsl,mpc5121-mscan";
0157 reg = <0x1300 0x80>;
0158 interrupts = <12 0x8>;
0159 clocks = <&clks MPC512x_CLK_BDLC>,
0160 <&clks MPC512x_CLK_IPS>,
0161 <&clks MPC512x_CLK_SYS>,
0162 <&clks MPC512x_CLK_REF>,
0163 <&clks MPC512x_CLK_MSCAN0_MCLK>;
0164 clock-names = "ipg", "ips", "sys", "ref", "mclk";
0165 };
0166
0167 can@1380 {
0168 compatible = "fsl,mpc5121-mscan";
0169 reg = <0x1380 0x80>;
0170 interrupts = <13 0x8>;
0171 clocks = <&clks MPC512x_CLK_BDLC>,
0172 <&clks MPC512x_CLK_IPS>,
0173 <&clks MPC512x_CLK_SYS>,
0174 <&clks MPC512x_CLK_REF>,
0175 <&clks MPC512x_CLK_MSCAN1_MCLK>;
0176 clock-names = "ipg", "ips", "sys", "ref", "mclk";
0177 };
0178
0179 sdhc@1500 {
0180 compatible = "fsl,mpc5121-sdhc";
0181 reg = <0x1500 0x100>;
0182 interrupts = <8 0x8>;
0183 dmas = <&dma0 30>;
0184 dma-names = "rx-tx";
0185 clocks = <&clks MPC512x_CLK_IPS>,
0186 <&clks MPC512x_CLK_SDHC>;
0187 clock-names = "ipg", "per";
0188 };
0189
0190 i2c@1700 {
0191 #address-cells = <1>;
0192 #size-cells = <0>;
0193 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
0194 reg = <0x1700 0x20>;
0195 interrupts = <9 0x8>;
0196 clocks = <&clks MPC512x_CLK_I2C>;
0197 clock-names = "ipg";
0198 };
0199
0200 i2c@1720 {
0201 #address-cells = <1>;
0202 #size-cells = <0>;
0203 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
0204 reg = <0x1720 0x20>;
0205 interrupts = <10 0x8>;
0206 clocks = <&clks MPC512x_CLK_I2C>;
0207 clock-names = "ipg";
0208 };
0209
0210 i2c@1740 {
0211 #address-cells = <1>;
0212 #size-cells = <0>;
0213 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
0214 reg = <0x1740 0x20>;
0215 interrupts = <11 0x8>;
0216 clocks = <&clks MPC512x_CLK_I2C>;
0217 clock-names = "ipg";
0218 };
0219
0220 i2ccontrol@1760 {
0221 compatible = "fsl,mpc5121-i2c-ctrl";
0222 reg = <0x1760 0x8>;
0223 };
0224
0225 axe@2000 {
0226 compatible = "fsl,mpc5121-axe";
0227 reg = <0x2000 0x100>;
0228 interrupts = <42 0x8>;
0229 clocks = <&clks MPC512x_CLK_AXE>;
0230 clock-names = "ipg";
0231 };
0232
0233 display@2100 {
0234 compatible = "fsl,mpc5121-diu";
0235 reg = <0x2100 0x100>;
0236 interrupts = <64 0x8>;
0237 clocks = <&clks MPC512x_CLK_DIU>;
0238 clock-names = "ipg";
0239 };
0240
0241 can@2300 {
0242 compatible = "fsl,mpc5121-mscan";
0243 reg = <0x2300 0x80>;
0244 interrupts = <90 0x8>;
0245 clocks = <&clks MPC512x_CLK_BDLC>,
0246 <&clks MPC512x_CLK_IPS>,
0247 <&clks MPC512x_CLK_SYS>,
0248 <&clks MPC512x_CLK_REF>,
0249 <&clks MPC512x_CLK_MSCAN2_MCLK>;
0250 clock-names = "ipg", "ips", "sys", "ref", "mclk";
0251 };
0252
0253 can@2380 {
0254 compatible = "fsl,mpc5121-mscan";
0255 reg = <0x2380 0x80>;
0256 interrupts = <91 0x8>;
0257 clocks = <&clks MPC512x_CLK_BDLC>,
0258 <&clks MPC512x_CLK_IPS>,
0259 <&clks MPC512x_CLK_SYS>,
0260 <&clks MPC512x_CLK_REF>,
0261 <&clks MPC512x_CLK_MSCAN3_MCLK>;
0262 clock-names = "ipg", "ips", "sys", "ref", "mclk";
0263 };
0264
0265 viu@2400 {
0266 compatible = "fsl,mpc5121-viu";
0267 reg = <0x2400 0x400>;
0268 interrupts = <67 0x8>;
0269 clocks = <&clks MPC512x_CLK_VIU>;
0270 clock-names = "ipg";
0271 };
0272
0273 mdio@2800 {
0274 compatible = "fsl,mpc5121-fec-mdio";
0275 reg = <0x2800 0x800>;
0276 #address-cells = <1>;
0277 #size-cells = <0>;
0278 clocks = <&clks MPC512x_CLK_FEC>;
0279 clock-names = "per";
0280 };
0281
0282 eth0: ethernet@2800 {
0283 device_type = "network";
0284 compatible = "fsl,mpc5121-fec";
0285 reg = <0x2800 0x800>;
0286 local-mac-address = [ 00 00 00 00 00 00 ];
0287 interrupts = <4 0x8>;
0288 clocks = <&clks MPC512x_CLK_FEC>;
0289 clock-names = "per";
0290 };
0291
0292 /* USB1 using external ULPI PHY */
0293 usb@3000 {
0294 compatible = "fsl,mpc5121-usb2-dr";
0295 reg = <0x3000 0x600>;
0296 #address-cells = <1>;
0297 #size-cells = <0>;
0298 interrupts = <43 0x8>;
0299 dr_mode = "otg";
0300 phy_type = "ulpi";
0301 clocks = <&clks MPC512x_CLK_USB1>;
0302 clock-names = "ipg";
0303 };
0304
0305 /* USB0 using internal UTMI PHY */
0306 usb@4000 {
0307 compatible = "fsl,mpc5121-usb2-dr";
0308 reg = <0x4000 0x600>;
0309 #address-cells = <1>;
0310 #size-cells = <0>;
0311 interrupts = <44 0x8>;
0312 dr_mode = "otg";
0313 phy_type = "utmi_wide";
0314 clocks = <&clks MPC512x_CLK_USB2>;
0315 clock-names = "ipg";
0316 };
0317
0318 /* IO control */
0319 ioctl@a000 {
0320 compatible = "fsl,mpc5121-ioctl";
0321 reg = <0xA000 0x1000>;
0322 };
0323
0324 /* LocalPlus controller */
0325 lpc@10000 {
0326 compatible = "fsl,mpc5121-lpc";
0327 reg = <0x10000 0x100>;
0328 };
0329
0330 sclpc@10100 {
0331 compatible = "fsl,mpc512x-lpbfifo";
0332 reg = <0x10100 0x50>;
0333 interrupts = <7 0x8>;
0334 dmas = <&dma0 26>;
0335 dma-names = "rx-tx";
0336 };
0337
0338 pata@10200 {
0339 compatible = "fsl,mpc5121-pata";
0340 reg = <0x10200 0x100>;
0341 interrupts = <5 0x8>;
0342 clocks = <&clks MPC512x_CLK_PATA>;
0343 clock-names = "ipg";
0344 };
0345
0346 /* 512x PSCs are not 52xx PSC compatible */
0347
0348 /* PSC0 */
0349 psc@11000 {
0350 compatible = "fsl,mpc5121-psc";
0351 reg = <0x11000 0x100>;
0352 interrupts = <40 0x8>;
0353 fsl,rx-fifo-size = <16>;
0354 fsl,tx-fifo-size = <16>;
0355 clocks = <&clks MPC512x_CLK_PSC0>,
0356 <&clks MPC512x_CLK_PSC0_MCLK>;
0357 clock-names = "ipg", "mclk";
0358 };
0359
0360 /* PSC1 */
0361 psc@11100 {
0362 compatible = "fsl,mpc5121-psc";
0363 reg = <0x11100 0x100>;
0364 interrupts = <40 0x8>;
0365 fsl,rx-fifo-size = <16>;
0366 fsl,tx-fifo-size = <16>;
0367 clocks = <&clks MPC512x_CLK_PSC1>,
0368 <&clks MPC512x_CLK_PSC1_MCLK>;
0369 clock-names = "ipg", "mclk";
0370 };
0371
0372 /* PSC2 */
0373 psc@11200 {
0374 compatible = "fsl,mpc5121-psc";
0375 reg = <0x11200 0x100>;
0376 interrupts = <40 0x8>;
0377 fsl,rx-fifo-size = <16>;
0378 fsl,tx-fifo-size = <16>;
0379 clocks = <&clks MPC512x_CLK_PSC2>,
0380 <&clks MPC512x_CLK_PSC2_MCLK>;
0381 clock-names = "ipg", "mclk";
0382 };
0383
0384 /* PSC3 */
0385 psc@11300 {
0386 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
0387 reg = <0x11300 0x100>;
0388 interrupts = <40 0x8>;
0389 fsl,rx-fifo-size = <16>;
0390 fsl,tx-fifo-size = <16>;
0391 clocks = <&clks MPC512x_CLK_PSC3>,
0392 <&clks MPC512x_CLK_PSC3_MCLK>;
0393 clock-names = "ipg", "mclk";
0394 };
0395
0396 /* PSC4 */
0397 psc@11400 {
0398 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
0399 reg = <0x11400 0x100>;
0400 interrupts = <40 0x8>;
0401 fsl,rx-fifo-size = <16>;
0402 fsl,tx-fifo-size = <16>;
0403 clocks = <&clks MPC512x_CLK_PSC4>,
0404 <&clks MPC512x_CLK_PSC4_MCLK>;
0405 clock-names = "ipg", "mclk";
0406 };
0407
0408 /* PSC5 */
0409 psc@11500 {
0410 compatible = "fsl,mpc5121-psc";
0411 reg = <0x11500 0x100>;
0412 interrupts = <40 0x8>;
0413 fsl,rx-fifo-size = <16>;
0414 fsl,tx-fifo-size = <16>;
0415 clocks = <&clks MPC512x_CLK_PSC5>,
0416 <&clks MPC512x_CLK_PSC5_MCLK>;
0417 clock-names = "ipg", "mclk";
0418 };
0419
0420 /* PSC6 */
0421 psc@11600 {
0422 compatible = "fsl,mpc5121-psc";
0423 reg = <0x11600 0x100>;
0424 interrupts = <40 0x8>;
0425 fsl,rx-fifo-size = <16>;
0426 fsl,tx-fifo-size = <16>;
0427 clocks = <&clks MPC512x_CLK_PSC6>,
0428 <&clks MPC512x_CLK_PSC6_MCLK>;
0429 clock-names = "ipg", "mclk";
0430 };
0431
0432 /* PSC7 */
0433 psc@11700 {
0434 compatible = "fsl,mpc5121-psc";
0435 reg = <0x11700 0x100>;
0436 interrupts = <40 0x8>;
0437 fsl,rx-fifo-size = <16>;
0438 fsl,tx-fifo-size = <16>;
0439 clocks = <&clks MPC512x_CLK_PSC7>,
0440 <&clks MPC512x_CLK_PSC7_MCLK>;
0441 clock-names = "ipg", "mclk";
0442 };
0443
0444 /* PSC8 */
0445 psc@11800 {
0446 compatible = "fsl,mpc5121-psc";
0447 reg = <0x11800 0x100>;
0448 interrupts = <40 0x8>;
0449 fsl,rx-fifo-size = <16>;
0450 fsl,tx-fifo-size = <16>;
0451 clocks = <&clks MPC512x_CLK_PSC8>,
0452 <&clks MPC512x_CLK_PSC8_MCLK>;
0453 clock-names = "ipg", "mclk";
0454 };
0455
0456 /* PSC9 */
0457 psc@11900 {
0458 compatible = "fsl,mpc5121-psc";
0459 reg = <0x11900 0x100>;
0460 interrupts = <40 0x8>;
0461 fsl,rx-fifo-size = <16>;
0462 fsl,tx-fifo-size = <16>;
0463 clocks = <&clks MPC512x_CLK_PSC9>,
0464 <&clks MPC512x_CLK_PSC9_MCLK>;
0465 clock-names = "ipg", "mclk";
0466 };
0467
0468 /* PSC10 */
0469 psc@11a00 {
0470 compatible = "fsl,mpc5121-psc";
0471 reg = <0x11a00 0x100>;
0472 interrupts = <40 0x8>;
0473 fsl,rx-fifo-size = <16>;
0474 fsl,tx-fifo-size = <16>;
0475 clocks = <&clks MPC512x_CLK_PSC10>,
0476 <&clks MPC512x_CLK_PSC10_MCLK>;
0477 clock-names = "ipg", "mclk";
0478 };
0479
0480 /* PSC11 */
0481 psc@11b00 {
0482 compatible = "fsl,mpc5121-psc";
0483 reg = <0x11b00 0x100>;
0484 interrupts = <40 0x8>;
0485 fsl,rx-fifo-size = <16>;
0486 fsl,tx-fifo-size = <16>;
0487 clocks = <&clks MPC512x_CLK_PSC11>,
0488 <&clks MPC512x_CLK_PSC11_MCLK>;
0489 clock-names = "ipg", "mclk";
0490 };
0491
0492 pscfifo@11f00 {
0493 compatible = "fsl,mpc5121-psc-fifo";
0494 reg = <0x11f00 0x100>;
0495 interrupts = <40 0x8>;
0496 clocks = <&clks MPC512x_CLK_PSC_FIFO>;
0497 clock-names = "ipg";
0498 };
0499
0500 dma0: dma@14000 {
0501 compatible = "fsl,mpc5121-dma";
0502 reg = <0x14000 0x1800>;
0503 interrupts = <65 0x8>;
0504 #dma-cells = <1>;
0505 };
0506 };
0507
0508 pci: pci@80008500 {
0509 compatible = "fsl,mpc5121-pci";
0510 device_type = "pci";
0511 interrupts = <1 0x8>;
0512 clock-frequency = <0>;
0513 #address-cells = <3>;
0514 #size-cells = <2>;
0515 #interrupt-cells = <1>;
0516 clocks = <&clks MPC512x_CLK_PCI>;
0517 clock-names = "ipg";
0518
0519 reg = <0x80008500 0x100 /* internal registers */
0520 0x80008300 0x8>; /* config space access registers */
0521 bus-range = <0x0 0x0>;
0522 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0523 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
0524 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
0525 };
0526 };
