0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Freescale Media5200 board Device Tree Source
0004 *
0005 * Copyright 2009 Secret Lab Technologies Ltd.
0006 * Grant Likely <grant.likely@secretlab.ca>
0007 * Steven Cavanagh <scavanagh@secretlab.ca>
0008 */
0009
0010 /include/ "mpc5200b.dtsi"
0011
0012 &gpt0 { fsl,has-wdt; };
0013
0014 / {
0015 model = "fsl,media5200";
0016 compatible = "fsl,media5200";
0017
0018 aliases {
0019 console = &console;
0020 ethernet0 = ð0;
0021 };
0022
0023 chosen {
0024 stdout-path = &console;
0025 };
0026
0027 cpus {
0028 PowerPC,5200@0 {
0029 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
0030 bus-frequency = <132000000>; // 132 MHz
0031 clock-frequency = <396000000>; // 396 MHz
0032 };
0033 };
0034
0035 memory@0 {
0036 reg = <0x00000000 0x08000000>; // 128MB RAM
0037 };
0038
0039 soc5200@f0000000 {
0040 bus-frequency = <132000000>;// 132 MHz
0041
0042 psc@2000 { // PSC1
0043 status = "disabled";
0044 };
0045
0046 psc@2200 { // PSC2
0047 status = "disabled";
0048 };
0049
0050 psc@2400 { // PSC3
0051 status = "disabled";
0052 };
0053
0054 psc@2600 { // PSC4
0055 status = "disabled";
0056 };
0057
0058 psc@2800 { // PSC5
0059 status = "disabled";
0060 };
0061
0062 // PSC6 in uart mode
0063 console: psc@2c00 { // PSC6
0064 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
0065 };
0066
0067 ethernet@3000 {
0068 phy-handle = <&phy0>;
0069 };
0070
0071 mdio@3000 {
0072 phy0: ethernet-phy@0 {
0073 reg = <0>;
0074 };
0075 };
0076
0077 usb@1000 {
0078 reg = <0x1000 0x100>;
0079 };
0080 };
0081
0082 pci@f0000d00 {
0083 interrupt-map-mask = <0xf800 0 0 7>;
0084 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
0085 0xc000 0 0 2 &media5200_fpga 0 3
0086 0xc000 0 0 3 &media5200_fpga 0 4
0087 0xc000 0 0 4 &media5200_fpga 0 5
0088
0089 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
0090 0xc800 0 0 2 &media5200_fpga 0 4
0091 0xc800 0 0 3 &media5200_fpga 0 5
0092 0xc800 0 0 4 &media5200_fpga 0 2
0093
0094 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
0095 0xd000 0 0 2 &media5200_fpga 0 5
0096
0097 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
0098 >;
0099 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000>,
0100 <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000>,
0101 <0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
0102 interrupt-parent = <&mpc5200_pic>;
0103 };
0104
0105 localbus {
0106 ranges = < 0 0 0xfc000000 0x02000000
0107 1 0 0xfe000000 0x02000000
0108 2 0 0xf0010000 0x00010000
0109 3 0 0xf0020000 0x00010000 >;
0110 flash@0,0 {
0111 compatible = "amd,am29lv28ml", "cfi-flash";
0112 reg = <0 0x0 0x2000000>; // 32 MB
0113 bank-width = <4>; // Width in bytes of the flash bank
0114 device-width = <2>; // Two devices on each bank
0115 };
0116
0117 flash@1,0 {
0118 compatible = "amd,am29lv28ml", "cfi-flash";
0119 reg = <1 0 0x2000000>; // 32 MB
0120 bank-width = <4>; // Width in bytes of the flash bank
0121 device-width = <2>; // Two devices on each bank
0122 };
0123
0124 media5200_fpga: fpga@2,0 {
0125 compatible = "fsl,media5200-fpga";
0126 interrupt-controller;
0127 #interrupt-cells = <2>; // 0:bank 1:id; no type field
0128 reg = <2 0 0x10000>;
0129
0130 interrupt-parent = <&mpc5200_pic>;
0131 interrupts = <0 0 3 // IRQ bank 0
0132 1 1 3>; // IRQ bank 1
0133 };
0134
0135 uart@3,0 {
0136 compatible = "ti,tl16c752bpt";
0137 reg = <3 0 0x10000>;
0138 interrupt-parent = <&media5200_fpga>;
0139 interrupts = <0 0 0 1>; // 2 irqs
0140 };
0141 };
0142 };
