0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Lite5200 board Device Tree Source
0004 *
0005 * Copyright 2006-2007 Secret Lab Technologies Ltd.
0006 * Grant Likely <grant.likely@secretlab.ca>
0007 */
0008
0009 /dts-v1/;
0010
0011 / {
0012 model = "fsl,lite5200";
0013 compatible = "fsl,lite5200";
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016 interrupt-parent = <&mpc5200_pic>;
0017
0018 cpus {
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021
0022 PowerPC,5200@0 {
0023 device_type = "cpu";
0024 reg = <0>;
0025 d-cache-line-size = <32>;
0026 i-cache-line-size = <32>;
0027 d-cache-size = <0x4000>; // L1, 16K
0028 i-cache-size = <0x4000>; // L1, 16K
0029 timebase-frequency = <0>; // from bootloader
0030 bus-frequency = <0>; // from bootloader
0031 clock-frequency = <0>; // from bootloader
0032 };
0033 };
0034
0035 memory@0 {
0036 device_type = "memory";
0037 reg = <0x00000000 0x04000000>; // 64MB
0038 };
0039
0040 soc5200@f0000000 {
0041 #address-cells = <1>;
0042 #size-cells = <1>;
0043 compatible = "fsl,mpc5200-immr";
0044 ranges = <0 0xf0000000 0x0000c000>;
0045 reg = <0xf0000000 0x00000100>;
0046 bus-frequency = <0>; // from bootloader
0047 system-frequency = <0>; // from bootloader
0048
0049 cdm@200 {
0050 compatible = "fsl,mpc5200-cdm";
0051 reg = <0x200 0x38>;
0052 };
0053
0054 mpc5200_pic: interrupt-controller@500 {
0055 // 5200 interrupts are encoded into two levels;
0056 interrupt-controller;
0057 #interrupt-cells = <3>;
0058 compatible = "fsl,mpc5200-pic";
0059 reg = <0x500 0x80>;
0060 };
0061
0062 timer@600 { // General Purpose Timer
0063 compatible = "fsl,mpc5200-gpt";
0064 reg = <0x600 0x10>;
0065 interrupts = <1 9 0>;
0066 fsl,has-wdt;
0067 };
0068
0069 timer@610 { // General Purpose Timer
0070 compatible = "fsl,mpc5200-gpt";
0071 reg = <0x610 0x10>;
0072 interrupts = <1 10 0>;
0073 };
0074
0075 timer@620 { // General Purpose Timer
0076 compatible = "fsl,mpc5200-gpt";
0077 reg = <0x620 0x10>;
0078 interrupts = <1 11 0>;
0079 };
0080
0081 timer@630 { // General Purpose Timer
0082 compatible = "fsl,mpc5200-gpt";
0083 reg = <0x630 0x10>;
0084 interrupts = <1 12 0>;
0085 };
0086
0087 timer@640 { // General Purpose Timer
0088 compatible = "fsl,mpc5200-gpt";
0089 reg = <0x640 0x10>;
0090 interrupts = <1 13 0>;
0091 };
0092
0093 timer@650 { // General Purpose Timer
0094 compatible = "fsl,mpc5200-gpt";
0095 reg = <0x650 0x10>;
0096 interrupts = <1 14 0>;
0097 };
0098
0099 timer@660 { // General Purpose Timer
0100 compatible = "fsl,mpc5200-gpt";
0101 reg = <0x660 0x10>;
0102 interrupts = <1 15 0>;
0103 };
0104
0105 timer@670 { // General Purpose Timer
0106 compatible = "fsl,mpc5200-gpt";
0107 reg = <0x670 0x10>;
0108 interrupts = <1 16 0>;
0109 };
0110
0111 rtc@800 { // Real time clock
0112 compatible = "fsl,mpc5200-rtc";
0113 reg = <0x800 0x100>;
0114 interrupts = <1 5 0 1 6 0>;
0115 };
0116
0117 can@900 {
0118 compatible = "fsl,mpc5200-mscan";
0119 interrupts = <2 17 0>;
0120 reg = <0x900 0x80>;
0121 };
0122
0123 can@980 {
0124 compatible = "fsl,mpc5200-mscan";
0125 interrupts = <2 18 0>;
0126 reg = <0x980 0x80>;
0127 };
0128
0129 gpio@b00 {
0130 compatible = "fsl,mpc5200-gpio";
0131 reg = <0xb00 0x40>;
0132 interrupts = <1 7 0>;
0133 gpio-controller;
0134 #gpio-cells = <2>;
0135 };
0136
0137 gpio@c00 {
0138 compatible = "fsl,mpc5200-gpio-wkup";
0139 reg = <0xc00 0x40>;
0140 interrupts = <1 8 0 0 3 0>;
0141 gpio-controller;
0142 #gpio-cells = <2>;
0143 };
0144
0145 spi@f00 {
0146 compatible = "fsl,mpc5200-spi";
0147 reg = <0xf00 0x20>;
0148 interrupts = <2 13 0 2 14 0>;
0149 };
0150
0151 usb@1000 {
0152 compatible = "fsl,mpc5200-ohci","ohci-be";
0153 reg = <0x1000 0xff>;
0154 interrupts = <2 6 0>;
0155 };
0156
0157 dma-controller@1200 {
0158 compatible = "fsl,mpc5200-bestcomm";
0159 reg = <0x1200 0x80>;
0160 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
0161 3 4 0 3 5 0 3 6 0 3 7 0
0162 3 8 0 3 9 0 3 10 0 3 11 0
0163 3 12 0 3 13 0 3 14 0 3 15 0>;
0164 };
0165
0166 xlb@1f00 {
0167 compatible = "fsl,mpc5200-xlb";
0168 reg = <0x1f00 0x100>;
0169 };
0170
0171 serial@2000 { // PSC1
0172 compatible = "fsl,mpc5200-psc-uart";
0173 cell-index = <0>;
0174 reg = <0x2000 0x100>;
0175 interrupts = <2 1 0>;
0176 };
0177
0178 // PSC2 in ac97 mode example
0179 //ac97@2200 { // PSC2
0180 // compatible = "fsl,mpc5200-psc-ac97";
0181 // cell-index = <1>;
0182 // reg = <0x2200 0x100>;
0183 // interrupts = <2 2 0>;
0184 //};
0185
0186 // PSC3 in CODEC mode example
0187 //i2s@2400 { // PSC3
0188 // compatible = "fsl,mpc5200-psc-i2s";
0189 // cell-index = <2>;
0190 // reg = <0x2400 0x100>;
0191 // interrupts = <2 3 0>;
0192 //};
0193
0194 // PSC4 in uart mode example
0195 //serial@2600 { // PSC4
0196 // compatible = "fsl,mpc5200-psc-uart";
0197 // cell-index = <3>;
0198 // reg = <0x2600 0x100>;
0199 // interrupts = <2 11 0>;
0200 //};
0201
0202 // PSC5 in uart mode example
0203 //serial@2800 { // PSC5
0204 // compatible = "fsl,mpc5200-psc-uart";
0205 // cell-index = <4>;
0206 // reg = <0x2800 0x100>;
0207 // interrupts = <2 12 0>;
0208 //};
0209
0210 // PSC6 in spi mode example
0211 //spi@2c00 { // PSC6
0212 // compatible = "fsl,mpc5200-psc-spi";
0213 // cell-index = <5>;
0214 // reg = <0x2c00 0x100>;
0215 // interrupts = <2 4 0>;
0216 //};
0217
0218 ethernet@3000 {
0219 compatible = "fsl,mpc5200-fec";
0220 reg = <0x3000 0x400>;
0221 local-mac-address = [ 00 00 00 00 00 00 ];
0222 interrupts = <2 5 0>;
0223 phy-handle = <&phy0>;
0224 };
0225
0226 mdio@3000 {
0227 #address-cells = <1>;
0228 #size-cells = <0>;
0229 compatible = "fsl,mpc5200-mdio";
0230 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
0231 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
0232
0233 phy0: ethernet-phy@0 {
0234 reg = <0>;
0235 };
0236 };
0237
0238 ata@3a00 {
0239 compatible = "fsl,mpc5200-ata";
0240 reg = <0x3a00 0x100>;
0241 interrupts = <2 7 0>;
0242 };
0243
0244 i2c@3d00 {
0245 #address-cells = <1>;
0246 #size-cells = <0>;
0247 compatible = "fsl,mpc5200-i2c","fsl-i2c";
0248 reg = <0x3d00 0x40>;
0249 interrupts = <2 15 0>;
0250 };
0251
0252 i2c@3d40 {
0253 #address-cells = <1>;
0254 #size-cells = <0>;
0255 compatible = "fsl,mpc5200-i2c","fsl-i2c";
0256 reg = <0x3d40 0x40>;
0257 interrupts = <2 16 0>;
0258
0259 eeprom@50 {
0260 compatible = "atmel,24c02";
0261 reg = <0x50>;
0262 };
0263 };
0264
0265 sram@8000 {
0266 compatible = "fsl,mpc5200-sram";
0267 reg = <0x8000 0x4000>;
0268 };
0269 };
0270
0271 pci@f0000d00 {
0272 #interrupt-cells = <1>;
0273 #size-cells = <2>;
0274 #address-cells = <3>;
0275 device_type = "pci";
0276 compatible = "fsl,mpc5200-pci";
0277 reg = <0xf0000d00 0x100>;
0278 interrupt-map-mask = <0xf800 0 0 7>;
0279 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
0280 0xc000 0 0 2 &mpc5200_pic 0 0 3
0281 0xc000 0 0 3 &mpc5200_pic 0 0 3
0282 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
0283 clock-frequency = <0>; // From boot loader
0284 interrupts = <2 8 0 2 9 0 2 10 0>;
0285 bus-range = <0 0>;
0286 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000>,
0287 <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000>,
0288 <0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
0289 };
0290
0291 localbus {
0292 compatible = "fsl,mpc5200-lpb","simple-bus";
0293 #address-cells = <2>;
0294 #size-cells = <1>;
0295
0296 ranges = <0 0 0xff000000 0x01000000>;
0297
0298 flash@0,0 {
0299 compatible = "amd,am29lv652d", "cfi-flash";
0300 reg = <0 0 0x01000000>;
0301 bank-width = <1>;
0302 };
0303 };
0304 };
