0001 /*
0002 * Device Tree Souce for Buffalo KuroboxHD
0003 *
0004 * Choose CONFIG_LINKSTATION to build a kernel for KuroboxHD, or use
0005 * the default configuration linkstation_defconfig.
0006 *
0007 * Based on sandpoint.dts
0008 *
0009 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
0010 * Copyright 2008 Freescale Semiconductor, Inc.
0011 *
0012 * This file is licensed under
0013 * the terms of the GNU General Public License version 2. This program
0014 * is licensed "as is" without any warranty of any kind, whether express
0015 * or implied.
0016
0017 XXXX add flash parts, rtc, ??
0018
0019 */
0020
0021 /dts-v1/;
0022
0023 / {
0024 model = "KuroboxHD";
0025 compatible = "linkstation";
0026 #address-cells = <1>;
0027 #size-cells = <1>;
0028
0029 aliases {
0030 serial0 = &serial0;
0031 serial1 = &serial1;
0032 pci0 = &pci0;
0033 };
0034
0035 cpus {
0036 #address-cells = <1>;
0037 #size-cells = <0>;
0038
0039 PowerPC,603e { /* Really 8241 */
0040 device_type = "cpu";
0041 reg = <0x0>;
0042 clock-frequency = <200000000>; /* Fixed by bootloader */
0043 timebase-frequency = <24391680>; /* Fixed by bootloader */
0044 bus-frequency = <0>; /* Fixed by bootloader */
0045 /* Following required by dtc but not used */
0046 i-cache-size = <0x4000>;
0047 d-cache-size = <0x4000>;
0048 };
0049 };
0050
0051 memory {
0052 device_type = "memory";
0053 reg = <0x0 0x4000000>;
0054 };
0055
0056 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
0057 #address-cells = <1>;
0058 #size-cells = <1>;
0059 device_type = "soc";
0060 compatible = "mpc10x";
0061 store-gathering = <0>; /* 0 == off, !0 == on */
0062 reg = <0x80000000 0x100000>;
0063 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
0064 0xfc000000 0xfc000000 0x100000 /* EUMB */
0065 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */
0066 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */
0067 0xfef00000 0xfef00000 0x100000>; /* pci iack */
0068
0069 i2c@80003000 {
0070 #address-cells = <1>;
0071 #size-cells = <0>;
0072 cell-index = <0>;
0073 compatible = "fsl-i2c";
0074 reg = <0x80003000 0x1000>;
0075 interrupts = <5 2>;
0076 interrupt-parent = <&mpic>;
0077
0078 rtc@32 {
0079 compatible = "ricoh,rs5c372a";
0080 reg = <0x32>;
0081 };
0082 };
0083
0084 serial0: serial@80004500 {
0085 cell-index = <0>;
0086 device_type = "serial";
0087 compatible = "fsl,ns16550", "ns16550";
0088 reg = <0x80004500 0x8>;
0089 clock-frequency = <97553800>;
0090 current-speed = <9600>;
0091 interrupts = <9 0>;
0092 interrupt-parent = <&mpic>;
0093 };
0094
0095 serial1: serial@80004600 {
0096 cell-index = <1>;
0097 device_type = "serial";
0098 compatible = "fsl,ns16550", "ns16550";
0099 reg = <0x80004600 0x8>;
0100 clock-frequency = <97553800>;
0101 current-speed = <57600>;
0102 interrupts = <10 0>;
0103 interrupt-parent = <&mpic>;
0104 };
0105
0106 mpic: interrupt-controller@80040000 {
0107 #interrupt-cells = <2>;
0108 #address-cells = <0>;
0109 device_type = "open-pic";
0110 compatible = "chrp,open-pic";
0111 interrupt-controller;
0112 reg = <0x80040000 0x40000>;
0113 };
0114
0115 pci0: pci@fec00000 {
0116 #address-cells = <3>;
0117 #size-cells = <2>;
0118 #interrupt-cells = <1>;
0119 device_type = "pci";
0120 compatible = "mpc10x-pci";
0121 reg = <0xfec00000 0x400000>;
0122 ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000
0123 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
0124 bus-range = <0 255>;
0125 clock-frequency = <133333333>;
0126 interrupt-parent = <&mpic>;
0127 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0128 interrupt-map = <
0129 /* IDSEL 11 - IRQ0 ETH */
0130 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
0131 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
0132 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
0133 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
0134 /* IDSEL 12 - IRQ1 IDE0 */
0135 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
0136 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
0137 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
0138 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
0139 /* IDSEL 14 - IRQ3 USB2.0 */
0140 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
0141 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
0142 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
0143 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
0144 >;
0145 };
0146 };
0147 };
