OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Keymile KMETER1 Device Tree Source
0004 *
0005 * 2008-2011 DENX Software Engineering GmbH
0006 */
0007
0008 /dts-v1/;
0009
0010 / {
0011 model = "KMETER1";
0012 compatible = "keymile,KMETER1";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 aliases {
0017 ethernet0 = &enet_piggy2;
0018 ethernet1 = &enet_estar1;
0019 ethernet2 = &enet_estar2;
0020 ethernet3 = &enet_eth1;
0021 ethernet4 = &enet_eth2;
0022 ethernet5 = &enet_eth3;
0023 ethernet6 = &enet_eth4;
0024 serial0 = &serial0;
0025 };
0026
0027 cpus {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030
0031 PowerPC,8360@0 {
0032 device_type = "cpu";
0033 reg = <0x0>;
0034 d-cache-line-size = <32>; // 32 bytes
0035 i-cache-line-size = <32>; // 32 bytes
0036 d-cache-size = <32768>; // L1, 32K
0037 i-cache-size = <32768>; // L1, 32K
0038 timebase-frequency = <0>; /* Filled in by U-Boot */
0039 bus-frequency = <0>; /* Filled in by U-Boot */
0040 clock-frequency = <0>; /* Filled in by U-Boot */
0041 };
0042 };
0043
0044 memory {
0045 device_type = "memory";
0046 reg = <0 0>; /* Filled in by U-Boot */
0047 };
0048
0049 soc8360@e0000000 {
0050 #address-cells = <1>;
0051 #size-cells = <1>;
0052 device_type = "soc";
0053 compatible = "fsl,mpc8360-immr", "simple-bus";
0054 ranges = <0x0 0xe0000000 0x00200000>;
0055 reg = <0xe0000000 0x00000200>;
0056 bus-frequency = <0>; /* Filled in by U-Boot */
0057
0058 pmc: power@b00 {
0059 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
0060 reg = <0xb00 0x100 0xa00 0x100>;
0061 interrupts = <80 0x8>;
0062 interrupt-parent = <&ipic>;
0063 };
0064
0065 i2c@3000 {
0066 #address-cells = <1>;
0067 #size-cells = <0>;
0068 cell-index = <0>;
0069 compatible = "fsl,mpc8313-i2c","fsl-i2c";
0070 reg = <0x3000 0x100>;
0071 interrupts = <14 0x8>;
0072 interrupt-parent = <&ipic>;
0073 clock-frequency = <400000>;
0074 };
0075
0076 serial0: serial@4500 {
0077 cell-index = <0>;
0078 device_type = "serial";
0079 compatible = "fsl,ns16550", "ns16550";
0080 reg = <0x4500 0x100>;
0081 clock-frequency = <264000000>;
0082 interrupts = <9 0x8>;
0083 interrupt-parent = <&ipic>;
0084 };
0085
0086 dma@82a8 {
0087 #address-cells = <1>;
0088 #size-cells = <1>;
0089 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
0090 reg = <0x82a8 4>;
0091 ranges = <0 0x8100 0x1a8>;
0092 interrupt-parent = <&ipic>;
0093 interrupts = <71 8>;
0094 cell-index = <0>;
0095 dma-channel@0 {
0096 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0097 reg = <0 0x80>;
0098 interrupt-parent = <&ipic>;
0099 interrupts = <71 8>;
0100 };
0101 dma-channel@80 {
0102 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0103 reg = <0x80 0x80>;
0104 interrupt-parent = <&ipic>;
0105 interrupts = <71 8>;
0106 };
0107 dma-channel@100 {
0108 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0109 reg = <0x100 0x80>;
0110 interrupt-parent = <&ipic>;
0111 interrupts = <71 8>;
0112 };
0113 dma-channel@180 {
0114 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
0115 reg = <0x180 0x28>;
0116 interrupt-parent = <&ipic>;
0117 interrupts = <71 8>;
0118 };
0119 };
0120
0121 ipic: pic@700 {
0122 #address-cells = <0>;
0123 #interrupt-cells = <2>;
0124 compatible = "fsl,pq2pro-pic", "fsl,ipic";
0125 interrupt-controller;
0126 reg = <0x700 0x100>;
0127 };
0128
0129 par_io@1400 {
0130 #address-cells = <1>;
0131 #size-cells = <0>;
0132 reg = <0x1400 0x100>;
0133 compatible = "fsl,mpc8360-par_io";
0134 num-ports = <7>;
0135
0136 qe_pio_c: gpio-controller@30 {
0137 #gpio-cells = <2>;
0138 compatible = "fsl,mpc8360-qe-pario-bank",
0139 "fsl,mpc8323-qe-pario-bank";
0140 reg = <0x1430 0x18>;
0141 gpio-controller;
0142 };
0143 pio_ucc1: ucc_pin@0 {
0144 reg = <0>;
0145
0146 pio-map = <
0147 /* port pin dir open_drain assignment has_irq */
0148 0 1 3 0 2 0 /* MDIO */
0149 0 2 1 0 1 0 /* MDC */
0150
0151 0 3 1 0 1 0 /* TxD0 */
0152 0 4 1 0 1 0 /* TxD1 */
0153 0 5 1 0 1 0 /* TxD2 */
0154 0 6 1 0 1 0 /* TxD3 */
0155 0 9 2 0 1 0 /* RxD0 */
0156 0 10 2 0 1 0 /* RxD1 */
0157 0 11 2 0 1 0 /* RxD2 */
0158 0 12 2 0 1 0 /* RxD3 */
0159 0 7 1 0 1 0 /* TX_EN */
0160 0 8 1 0 1 0 /* TX_ER */
0161 0 15 2 0 1 0 /* RX_DV */
0162 0 16 2 0 1 0 /* RX_ER */
0163 0 0 2 0 1 0 /* RX_CLK */
0164 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
0165 2 8 2 0 1 0 /* GTX125 - CLK9 */
0166 >;
0167 };
0168
0169 pio_ucc2: ucc_pin@1 {
0170 reg = <1>;
0171
0172 pio-map = <
0173 /* port pin dir open_drain assignment has_irq */
0174 0 1 3 0 2 0 /* MDIO */
0175 0 2 1 0 1 0 /* MDC */
0176
0177 0 17 1 0 1 0 /* TxD0 */
0178 0 18 1 0 1 0 /* TxD1 */
0179 0 19 1 0 1 0 /* TxD2 */
0180 0 20 1 0 1 0 /* TxD3 */
0181 0 23 2 0 1 0 /* RxD0 */
0182 0 24 2 0 1 0 /* RxD1 */
0183 0 25 2 0 1 0 /* RxD2 */
0184 0 26 2 0 1 0 /* RxD3 */
0185 0 21 1 0 1 0 /* TX_EN */
0186 0 22 1 0 1 0 /* TX_ER */
0187 0 29 2 0 1 0 /* RX_DV */
0188 0 30 2 0 1 0 /* RX_ER */
0189 0 31 2 0 1 0 /* RX_CLK */
0190 2 2 1 0 2 0 /* GTX_CLK - CLK3 */
0191 2 3 2 0 1 0 /* GTX125 - CLK4 */
0192 >;
0193 };
0194
0195 pio_ucc4: ucc_pin@3 {
0196 reg = <3>;
0197
0198 pio-map = <
0199 /* port pin dir open_drain assignment has_irq */
0200 0 1 3 0 2 0 /* MDIO */
0201 0 2 1 0 1 0 /* MDC */
0202
0203 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
0204 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
0205 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
0206 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
0207 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
0208 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
0209 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
0210
0211 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
0212 >;
0213 };
0214
0215 pio_ucc5: ucc_pin@4 {
0216 reg = <4>;
0217
0218 pio-map = <
0219 /* port pin dir open_drain assignment has_irq */
0220 0 1 3 0 2 0 /* MDIO */
0221 0 2 1 0 1 0 /* MDC */
0222
0223 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
0224 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
0225 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
0226 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
0227 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
0228 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
0229 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
0230 >;
0231 };
0232
0233 pio_ucc6: ucc_pin@5 {
0234 reg = <5>;
0235
0236 pio-map = <
0237 /* port pin dir open_drain assignment has_irq */
0238 0 1 3 0 2 0 /* MDIO */
0239 0 2 1 0 1 0 /* MDC */
0240
0241 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
0242 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
0243 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
0244 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
0245 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
0246 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
0247 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
0248 >;
0249 };
0250
0251 pio_ucc7: ucc_pin@6 {
0252 reg = <6>;
0253
0254 pio-map = <
0255 /* port pin dir open_drain assignment has_irq */
0256 0 1 3 0 2 0 /* MDIO */
0257 0 2 1 0 1 0 /* MDC */
0258
0259 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
0260 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
0261 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
0262 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
0263 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
0264 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
0265 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
0266 >;
0267 };
0268
0269 pio_ucc8: ucc_pin@7 {
0270 reg = <7>;
0271
0272 pio-map = <
0273 /* port pin dir open_drain assignment has_irq */
0274 0 1 3 0 2 0 /* MDIO */
0275 0 2 1 0 1 0 /* MDC */
0276
0277 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
0278 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
0279 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
0280 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
0281 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
0282 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
0283 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
0284
0285 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
0286 >;
0287 };
0288
0289 };
0290
0291 qe@100000 {
0292 #address-cells = <1>;
0293 #size-cells = <1>;
0294 compatible = "fsl,qe";
0295 ranges = <0x0 0x100000 0x100000>;
0296 reg = <0x100000 0x480>;
0297 clock-frequency = <0>; /* Filled in by U-Boot */
0298 brg-frequency = <0>; /* Filled in by U-Boot */
0299 bus-frequency = <0>; /* Filled in by U-Boot */
0300
0301 muram@10000 {
0302 #address-cells = <1>;
0303 #size-cells = <1>;
0304 compatible = "fsl,qe-muram", "fsl,cpm-muram";
0305 ranges = <0x0 0x00010000 0x0000c000>;
0306
0307 data-only@0 {
0308 compatible = "fsl,qe-muram-data",
0309 "fsl,cpm-muram-data";
0310 reg = <0x0 0xc000>;
0311 };
0312 };
0313
0314 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
0315 enet_estar1: ucc@2000 {
0316 device_type = "network";
0317 compatible = "ucc_geth";
0318 cell-index = <1>;
0319 reg = <0x2000 0x200>;
0320 interrupts = <32>;
0321 interrupt-parent = <&qeic>;
0322 local-mac-address = [ 00 00 00 00 00 00 ];
0323 rx-clock-name = "none";
0324 tx-clock-name = "clk9";
0325 phy-handle = <&phy_estar1>;
0326 phy-connection-type = "rgmii-id";
0327 pio-handle = <&pio_ucc1>;
0328 };
0329
0330 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
0331 enet_estar2: ucc@3000 {
0332 device_type = "network";
0333 compatible = "ucc_geth";
0334 cell-index = <2>;
0335 reg = <0x3000 0x200>;
0336 interrupts = <33>;
0337 interrupt-parent = <&qeic>;
0338 local-mac-address = [ 00 00 00 00 00 00 ];
0339 rx-clock-name = "none";
0340 tx-clock-name = "clk4";
0341 phy-handle = <&phy_estar2>;
0342 phy-connection-type = "rgmii-id";
0343 pio-handle = <&pio_ucc2>;
0344 };
0345
0346 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
0347 enet_piggy2: ucc@3200 {
0348 device_type = "network";
0349 compatible = "ucc_geth";
0350 cell-index = <4>;
0351 reg = <0x3200 0x200>;
0352 interrupts = <35>;
0353 interrupt-parent = <&qeic>;
0354 local-mac-address = [ 00 00 00 00 00 00 ];
0355 rx-clock-name = "none";
0356 tx-clock-name = "clk17";
0357 phy-handle = <&phy_piggy2>;
0358 phy-connection-type = "rmii";
0359 pio-handle = <&pio_ucc4>;
0360 };
0361
0362 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
0363 enet_eth1: ucc@2400 {
0364 device_type = "network";
0365 compatible = "ucc_geth";
0366 cell-index = <5>;
0367 reg = <0x2400 0x200>;
0368 interrupts = <40>;
0369 interrupt-parent = <&qeic>;
0370 local-mac-address = [ 00 00 00 00 00 00 ];
0371 rx-clock-name = "none";
0372 tx-clock-name = "clk16";
0373 phy-handle = <&phy_eth1>;
0374 phy-connection-type = "rmii";
0375 pio-handle = <&pio_ucc5>;
0376 };
0377
0378 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
0379 enet_eth2: ucc@3400 {
0380 device_type = "network";
0381 compatible = "ucc_geth";
0382 cell-index = <6>;
0383 reg = <0x3400 0x200>;
0384 interrupts = <41>;
0385 interrupt-parent = <&qeic>;
0386 local-mac-address = [ 00 00 00 00 00 00 ];
0387 rx-clock-name = "none";
0388 tx-clock-name = "clk16";
0389 phy-handle = <&phy_eth2>;
0390 phy-connection-type = "rmii";
0391 pio-handle = <&pio_ucc6>;
0392 };
0393
0394 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
0395 enet_eth3: ucc@2600 {
0396 device_type = "network";
0397 compatible = "ucc_geth";
0398 cell-index = <7>;
0399 reg = <0x2600 0x200>;
0400 interrupts = <42>;
0401 interrupt-parent = <&qeic>;
0402 local-mac-address = [ 00 00 00 00 00 00 ];
0403 rx-clock-name = "none";
0404 tx-clock-name = "clk16";
0405 phy-handle = <&phy_eth3>;
0406 phy-connection-type = "rmii";
0407 pio-handle = <&pio_ucc7>;
0408 };
0409
0410 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
0411 enet_eth4: ucc@3600 {
0412 device_type = "network";
0413 compatible = "ucc_geth";
0414 cell-index = <8>;
0415 reg = <0x3600 0x200>;
0416 interrupts = <43>;
0417 interrupt-parent = <&qeic>;
0418 local-mac-address = [ 00 00 00 00 00 00 ];
0419 rx-clock-name = "none";
0420 tx-clock-name = "clk16";
0421 phy-handle = <&phy_eth4>;
0422 phy-connection-type = "rmii";
0423 pio-handle = <&pio_ucc8>;
0424 };
0425
0426 mdio@3320 {
0427 #address-cells = <1>;
0428 #size-cells = <0>;
0429 reg = <0x3320 0x18>;
0430 compatible = "fsl,ucc-mdio";
0431
0432 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
0433 phy_piggy2: ethernet-phy@0 {
0434 reg = <0x0>;
0435 };
0436
0437 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
0438 phy_eth1: ethernet-phy@8 {
0439 reg = <0x08>;
0440 };
0441
0442 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
0443 phy_eth2: ethernet-phy@9 {
0444 reg = <0x09>;
0445 };
0446
0447 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
0448 phy_eth3: ethernet-phy@a {
0449 reg = <0x0a>;
0450 };
0451
0452 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
0453 phy_eth4: ethernet-phy@b {
0454 reg = <0x0b>;
0455 };
0456
0457 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
0458 phy_estar1: ethernet-phy@10 {
0459 interrupt-parent = <&ipic>;
0460 interrupts = <17 0x8>;
0461 reg = <0x10>;
0462 };
0463
0464 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
0465 phy_estar2: ethernet-phy@11 {
0466 interrupt-parent = <&ipic>;
0467 interrupts = <18 0x8>;
0468 reg = <0x11>;
0469 };
0470 };
0471
0472 qeic: interrupt-controller@80 {
0473 interrupt-controller;
0474 compatible = "fsl,qe-ic";
0475 #address-cells = <0>;
0476 #interrupt-cells = <1>;
0477 reg = <0x80 0x80>;
0478 big-endian;
0479 interrupts = <
0480 32 0x8
0481 33 0x8
0482 34 0x8
0483 35 0x8
0484 40 0x8
0485 41 0x8
0486 42 0x8
0487 43 0x8
0488 >;
0489 interrupt-parent = <&ipic>;
0490 };
0491 };
0492 };
0493
0494 localbus@e0005000 {
0495 #address-cells = <2>;
0496 #size-cells = <1>;
0497 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
0498 "simple-bus";
0499 reg = <0xe0005000 0xd8>;
0500 ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */
0501 1 0 0xe8000000 0x01000000 /* LB 1 */
0502 3 0 0xa0000000 0x10000000>; /* LB 3 */
0503
0504 flash@0,0 {
0505 compatible = "cfi-flash";
0506 reg = <0 0 0x04000000>;
0507 #address-cells = <1>;
0508 #size-cells = <1>;
0509 bank-width = <2>;
0510 partition@0 { /* 768KB */
0511 label = "u-boot";
0512 reg = <0 0xC0000>;
0513 };
0514 partition@c0000 { /* 128KB */
0515 label = "env";
0516 reg = <0xC0000 0x20000>;
0517 };
0518 partition@e0000 { /* 128KB */
0519 label = "envred";
0520 reg = <0xE0000 0x20000>;
0521 };
0522 partition@100000 { /* 64512KB */
0523 label = "ubi0";
0524 reg = <0x100000 0x3F00000>;
0525 };
0526 };
0527 };
0528 };
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