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0001 /*
0002  * Device Tree Source for IBM Embedded PPC 476 Platform
0003  *
0004  * Copyright 2010 Torez Smith, IBM Corporation.
0005  *
0006  * Based on earlier code:
0007  *     Copyright (c) 2006, 2007 IBM Corp.
0008  *     Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
0009  *
0010  * This file is licensed under the terms of the GNU General Public
0011  * License version 2.  This program is licensed "as is" without
0012  * any warranty of any kind, whether express or implied.
0013  */
0014 
0015 /dts-v1/;
0016 
0017 /memreserve/ 0x01f00000 0x00100000;
0018 
0019 / {
0020         #address-cells = <2>;
0021         #size-cells = <1>;
0022         model = "ibm,iss-4xx";
0023         compatible = "ibm,iss-4xx";
0024         dcr-parent = <&{/cpus/cpu@0}>;
0025 
0026         aliases {
0027                 serial0 = &UART0;
0028         };
0029 
0030         cpus {
0031                 #address-cells = <1>;
0032                 #size-cells = <0>;
0033 
0034                 cpu@0 {
0035                         device_type = "cpu";
0036                         model = "PowerPC,4xx"; // real CPU changed in sim
0037                         reg = <0>;
0038                         clock-frequency = <100000000>; // 100Mhz :-)
0039                         timebase-frequency = <100000000>;
0040                         i-cache-line-size = <32>;
0041                         d-cache-line-size = <32>;
0042                         i-cache-size = <32768>;
0043                         d-cache-size = <32768>;
0044                         dcr-controller;
0045                         dcr-access-method = "native";
0046                         status = "okay";
0047                 };
0048                 cpu@1 {
0049                         device_type = "cpu";
0050                         model = "PowerPC,4xx"; // real CPU changed in sim
0051                         reg = <1>;
0052                         clock-frequency = <100000000>; // 100Mhz :-)
0053                         timebase-frequency = <100000000>;
0054                         i-cache-line-size = <32>;
0055                         d-cache-line-size = <32>;
0056                         i-cache-size = <32768>;
0057                         d-cache-size = <32768>;
0058                         dcr-controller;
0059                         dcr-access-method = "native";
0060                         status = "disabled";
0061                         enable-method = "spin-table";
0062                         cpu-release-addr = <0 0x01f00100>;
0063                 };
0064                 cpu@2 {
0065                         device_type = "cpu";
0066                         model = "PowerPC,4xx"; // real CPU changed in sim
0067                         reg = <2>;
0068                         clock-frequency = <100000000>; // 100Mhz :-)
0069                         timebase-frequency = <100000000>;
0070                         i-cache-line-size = <32>;
0071                         d-cache-line-size = <32>;
0072                         i-cache-size = <32768>;
0073                         d-cache-size = <32768>;
0074                         dcr-controller;
0075                         dcr-access-method = "native";
0076                         status = "disabled";
0077                         enable-method = "spin-table";
0078                         cpu-release-addr = <0 0x01f00200>;
0079                 };
0080                 cpu@3 {
0081                         device_type = "cpu";
0082                         model = "PowerPC,4xx"; // real CPU changed in sim
0083                         reg = <3>;
0084                         clock-frequency = <100000000>; // 100Mhz :-)
0085                         timebase-frequency = <100000000>;
0086                         i-cache-line-size = <32>;
0087                         d-cache-line-size = <32>;
0088                         i-cache-size = <32768>;
0089                         d-cache-size = <32768>;
0090                         dcr-controller;
0091                         dcr-access-method = "native";
0092                         status = "disabled";
0093                         enable-method = "spin-table";
0094                         cpu-release-addr = <0 0x01f00300>;
0095                 };
0096         };
0097 
0098         memory {
0099                 device_type = "memory";
0100                 reg =  <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
0101 
0102         };
0103 
0104         MPIC: interrupt-controller {
0105                 compatible = "chrp,open-pic";
0106                 interrupt-controller;
0107                 dcr-reg = <0xffc00000 0x00030000>;
0108                 #address-cells = <0>;
0109                 #size-cells = <0>;
0110                 #interrupt-cells = <2>;
0111 
0112         };
0113 
0114         plb {
0115                 compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
0116                 #address-cells = <2>;
0117                 #size-cells = <1>;
0118                 ranges;
0119                 clock-frequency = <0>; // Filled in by zImage
0120 
0121                 POB0: opb {
0122                         compatible = "ibm,opb-4xx", "ibm,opb";
0123                         #address-cells = <1>;
0124                         #size-cells = <1>;
0125                         /* Wish there was a nicer way of specifying a full 32-bit
0126                            range */
0127                         ranges = <0x00000000 0x00000001 0x00000000 0x80000000
0128                                   0x80000000 0x00000001 0x80000000 0x80000000>;
0129                         clock-frequency = <0>; // Filled in by zImage
0130                         UART0: serial@40000200 {
0131                                 device_type = "serial";
0132                                 compatible = "ns16550a";
0133                                 reg = <0x40000200 0x00000008>;
0134                                 virtual-reg = <0xe0000200>;
0135                                 clock-frequency = <11059200>;
0136                                 current-speed = <115200>;
0137                                 interrupt-parent = <&MPIC>;
0138                                 interrupts = <0x0 0x2>;
0139                         };
0140                 };
0141         };
0142 
0143         nvrtc {
0144                 compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
0145                 reg = <0 0xEF703000 0x2000>;
0146         };
0147         iss-block {
0148                 compatible = "ibm,iss-sim-block-device";
0149                 reg = <0 0xEF701000 0x1000>;
0150         };
0151 
0152         chosen {
0153                 stdout-path = "/plb/opb/serial@40000200";
0154         };
0155 };