0001 /*
0002 * T4240 Silicon/SoC Device Tree Source (pre include)
0003 *
0004 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 /dts-v1/;
0036
0037 /include/ "e6500_power_isa.dtsi"
0038
0039 / {
0040 compatible = "fsl,T4240";
0041 #address-cells = <2>;
0042 #size-cells = <2>;
0043 interrupt-parent = <&mpic>;
0044
0045 aliases {
0046 ccsr = &soc;
0047 dcsr = &dcsr;
0048
0049 serial0 = &serial0;
0050 serial1 = &serial1;
0051 serial2 = &serial2;
0052 serial3 = &serial3;
0053 crypto = &crypto;
0054
0055 pci0 = &pci0;
0056 pci1 = &pci1;
0057 pci2 = &pci2;
0058 pci3 = &pci3;
0059 usb0 = &usb0;
0060 usb1 = &usb1;
0061 dma0 = &dma0;
0062 dma1 = &dma1;
0063 dma2 = &dma2;
0064 sdhc = &sdhc;
0065
0066 fman0 = &fman0;
0067 fman1 = &fman1;
0068 ethernet0 = &enet0;
0069 ethernet1 = &enet1;
0070 ethernet2 = &enet2;
0071 ethernet3 = &enet3;
0072 ethernet4 = &enet4;
0073 ethernet5 = &enet5;
0074 ethernet6 = &enet6;
0075 ethernet7 = &enet7;
0076 ethernet8 = &enet8;
0077 ethernet9 = &enet9;
0078 ethernet10 = &enet10;
0079 ethernet11 = &enet11;
0080 ethernet12 = &enet12;
0081 ethernet13 = &enet13;
0082 ethernet14 = &enet14;
0083 ethernet15 = &enet15;
0084 };
0085
0086 cpus {
0087 #address-cells = <1>;
0088 #size-cells = <0>;
0089
0090 cpu0: PowerPC,e6500@0 {
0091 device_type = "cpu";
0092 reg = <0 1>;
0093 clocks = <&clockgen 1 0>;
0094 next-level-cache = <&L2_1>;
0095 fsl,portid-mapping = <0x80000000>;
0096 };
0097 cpu1: PowerPC,e6500@2 {
0098 device_type = "cpu";
0099 reg = <2 3>;
0100 clocks = <&clockgen 1 0>;
0101 next-level-cache = <&L2_1>;
0102 fsl,portid-mapping = <0x80000000>;
0103 };
0104 cpu2: PowerPC,e6500@4 {
0105 device_type = "cpu";
0106 reg = <4 5>;
0107 clocks = <&clockgen 1 0>;
0108 next-level-cache = <&L2_1>;
0109 fsl,portid-mapping = <0x80000000>;
0110 };
0111 cpu3: PowerPC,e6500@6 {
0112 device_type = "cpu";
0113 reg = <6 7>;
0114 clocks = <&clockgen 1 0>;
0115 next-level-cache = <&L2_1>;
0116 fsl,portid-mapping = <0x80000000>;
0117 };
0118 cpu4: PowerPC,e6500@8 {
0119 device_type = "cpu";
0120 reg = <8 9>;
0121 clocks = <&clockgen 1 1>;
0122 next-level-cache = <&L2_2>;
0123 fsl,portid-mapping = <0x40000000>;
0124 };
0125 cpu5: PowerPC,e6500@10 {
0126 device_type = "cpu";
0127 reg = <10 11>;
0128 clocks = <&clockgen 1 1>;
0129 next-level-cache = <&L2_2>;
0130 fsl,portid-mapping = <0x40000000>;
0131 };
0132 cpu6: PowerPC,e6500@12 {
0133 device_type = "cpu";
0134 reg = <12 13>;
0135 clocks = <&clockgen 1 1>;
0136 next-level-cache = <&L2_2>;
0137 fsl,portid-mapping = <0x40000000>;
0138 };
0139 cpu7: PowerPC,e6500@14 {
0140 device_type = "cpu";
0141 reg = <14 15>;
0142 clocks = <&clockgen 1 1>;
0143 next-level-cache = <&L2_2>;
0144 fsl,portid-mapping = <0x40000000>;
0145 };
0146 cpu8: PowerPC,e6500@16 {
0147 device_type = "cpu";
0148 reg = <16 17>;
0149 clocks = <&clockgen 1 2>;
0150 next-level-cache = <&L2_3>;
0151 fsl,portid-mapping = <0x20000000>;
0152 };
0153 cpu9: PowerPC,e6500@18 {
0154 device_type = "cpu";
0155 reg = <18 19>;
0156 clocks = <&clockgen 1 2>;
0157 next-level-cache = <&L2_3>;
0158 fsl,portid-mapping = <0x20000000>;
0159 };
0160 cpu10: PowerPC,e6500@20 {
0161 device_type = "cpu";
0162 reg = <20 21>;
0163 clocks = <&clockgen 1 2>;
0164 next-level-cache = <&L2_3>;
0165 fsl,portid-mapping = <0x20000000>;
0166 };
0167 cpu11: PowerPC,e6500@22 {
0168 device_type = "cpu";
0169 reg = <22 23>;
0170 clocks = <&clockgen 1 2>;
0171 next-level-cache = <&L2_3>;
0172 fsl,portid-mapping = <0x20000000>;
0173 };
0174 };
0175 };
