0001 /*
0002 * T4240RDB Device Tree Source
0003 *
0004 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 /include/ "t4240si-pre.dtsi"
0036
0037 / {
0038 model = "fsl,T4240RDB";
0039 compatible = "fsl,T4240RDB";
0040 #address-cells = <2>;
0041 #size-cells = <2>;
0042 interrupt-parent = <&mpic>;
0043
0044 aliases {
0045 sgmii_phy21 = &sgmiiphy21;
0046 sgmii_phy22 = &sgmiiphy22;
0047 sgmii_phy23 = &sgmiiphy23;
0048 sgmii_phy24 = &sgmiiphy24;
0049 sgmii_phy41 = &sgmiiphy41;
0050 sgmii_phy42 = &sgmiiphy42;
0051 sgmii_phy43 = &sgmiiphy43;
0052 sgmii_phy44 = &sgmiiphy44;
0053 };
0054
0055 ifc: localbus@ffe124000 {
0056 reg = <0xf 0xfe124000 0 0x2000>;
0057 ranges = <0 0 0xf 0xe8000000 0x08000000
0058 2 0 0xf 0xff800000 0x00010000
0059 3 0 0xf 0xffdf0000 0x00008000>;
0060
0061 nor@0,0 {
0062 #address-cells = <1>;
0063 #size-cells = <1>;
0064 compatible = "cfi-flash";
0065 reg = <0x0 0x0 0x8000000>;
0066
0067 bank-width = <2>;
0068 device-width = <1>;
0069 };
0070
0071 nand@2,0 {
0072 #address-cells = <1>;
0073 #size-cells = <1>;
0074 compatible = "fsl,ifc-nand";
0075 reg = <0x2 0x0 0x10000>;
0076 };
0077 };
0078
0079 memory {
0080 device_type = "memory";
0081 };
0082
0083 reserved-memory {
0084 #address-cells = <2>;
0085 #size-cells = <2>;
0086 ranges;
0087
0088 bman_fbpr: bman-fbpr {
0089 size = <0 0x1000000>;
0090 alignment = <0 0x1000000>;
0091 };
0092 qman_fqd: qman-fqd {
0093 size = <0 0x400000>;
0094 alignment = <0 0x400000>;
0095 };
0096 qman_pfdr: qman-pfdr {
0097 size = <0 0x2000000>;
0098 alignment = <0 0x2000000>;
0099 };
0100 };
0101
0102 dcsr: dcsr@f00000000 {
0103 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
0104 };
0105
0106 bportals: bman-portals@ff4000000 {
0107 ranges = <0x0 0xf 0xf4000000 0x2000000>;
0108 };
0109
0110 qportals: qman-portals@ff6000000 {
0111 ranges = <0x0 0xf 0xf6000000 0x2000000>;
0112 };
0113
0114 soc: soc@ffe000000 {
0115 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
0116 reg = <0xf 0xfe000000 0 0x00001000>;
0117 spi@110000 {
0118 flash@0 {
0119 #address-cells = <1>;
0120 #size-cells = <1>;
0121 compatible = "sst,sst25wf040", "jedec,spi-nor";
0122 reg = <0>;
0123 spi-max-frequency = <40000000>; /* input clock */
0124 };
0125 };
0126
0127 i2c@118000 {
0128 hwmon@2f {
0129 compatible = "winbond,w83793";
0130 reg = <0x2f>;
0131 };
0132 eeprom@52 {
0133 compatible = "atmel,24c256";
0134 reg = <0x52>;
0135 };
0136 eeprom@54 {
0137 compatible = "atmel,24c256";
0138 reg = <0x54>;
0139 };
0140 eeprom@56 {
0141 compatible = "atmel,24c256";
0142 reg = <0x56>;
0143 };
0144 rtc@68 {
0145 compatible = "dallas,ds1374";
0146 reg = <0x68>;
0147 };
0148 };
0149
0150 sdhc@114000 {
0151 voltage-ranges = <1800 1800 3300 3300>;
0152 };
0153
0154 fman@400000 {
0155 ethernet@e0000 {
0156 phy-handle = <&sgmiiphy21>;
0157 phy-connection-type = "sgmii";
0158 };
0159
0160 ethernet@e2000 {
0161 phy-handle = <&sgmiiphy22>;
0162 phy-connection-type = "sgmii";
0163 };
0164
0165 ethernet@e4000 {
0166 phy-handle = <&sgmiiphy23>;
0167 phy-connection-type = "sgmii";
0168 };
0169
0170 ethernet@e6000 {
0171 phy-handle = <&sgmiiphy24>;
0172 phy-connection-type = "sgmii";
0173 };
0174
0175 ethernet@e8000 {
0176 status = "disabled";
0177 };
0178
0179 ethernet@ea000 {
0180 status = "disabled";
0181 };
0182
0183 ethernet@f0000 {
0184 phy-handle = <&xfiphy1>;
0185 phy-connection-type = "xgmii";
0186 };
0187
0188 ethernet@f2000 {
0189 phy-handle = <&xfiphy2>;
0190 phy-connection-type = "xgmii";
0191 };
0192 };
0193
0194 fman@500000 {
0195 ethernet@e0000 {
0196 phy-handle = <&sgmiiphy41>;
0197 phy-connection-type = "sgmii";
0198 };
0199
0200 ethernet@e2000 {
0201 phy-handle = <&sgmiiphy42>;
0202 phy-connection-type = "sgmii";
0203 };
0204
0205 ethernet@e4000 {
0206 phy-handle = <&sgmiiphy43>;
0207 phy-connection-type = "sgmii";
0208 };
0209
0210 ethernet@e6000 {
0211 phy-handle = <&sgmiiphy44>;
0212 phy-connection-type = "sgmii";
0213 };
0214
0215 ethernet@e8000 {
0216 status = "disabled";
0217 };
0218
0219 ethernet@ea000 {
0220 status = "disabled";
0221 };
0222
0223 ethernet@f0000 {
0224 phy-handle = <&xfiphy3>;
0225 phy-connection-type = "xgmii";
0226 };
0227
0228 ethernet@f2000 {
0229 phy-handle = <&xfiphy4>;
0230 phy-connection-type = "xgmii";
0231 };
0232
0233 mdio@fc000 {
0234 sgmiiphy21: ethernet-phy@0 {
0235 reg = <0x0>;
0236 };
0237
0238 sgmiiphy22: ethernet-phy@1 {
0239 reg = <0x1>;
0240 };
0241
0242 sgmiiphy23: ethernet-phy@2 {
0243 reg = <0x2>;
0244 };
0245
0246 sgmiiphy24: ethernet-phy@3 {
0247 reg = <0x3>;
0248 };
0249
0250 sgmiiphy41: ethernet-phy@4 {
0251 reg = <0x4>;
0252 };
0253
0254 sgmiiphy42: ethernet-phy@5 {
0255 reg = <0x5>;
0256 };
0257
0258 sgmiiphy43: ethernet-phy@6 {
0259 reg = <0x6>;
0260 };
0261
0262 sgmiiphy44: ethernet-phy@7 {
0263 reg = <0x7>;
0264 };
0265 };
0266
0267 mdio@fd000 {
0268 xfiphy1: ethernet-phy@10 {
0269 compatible = "ethernet-phy-id13e5.1002";
0270 reg = <0x10>;
0271 };
0272
0273 xfiphy2: ethernet-phy@11 {
0274 compatible = "ethernet-phy-id13e5.1002";
0275 reg = <0x11>;
0276 };
0277
0278 xfiphy3: ethernet-phy@13 {
0279 compatible = "ethernet-phy-id13e5.1002";
0280 reg = <0x13>;
0281 };
0282
0283 xfiphy4: ethernet-phy@12 {
0284 compatible = "ethernet-phy-id13e5.1002";
0285 reg = <0x12>;
0286 };
0287 };
0288 };
0289 };
0290
0291 pci0: pcie@ffe240000 {
0292 reg = <0xf 0xfe240000 0 0x10000>;
0293 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0294 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
0295 pcie@0 {
0296 ranges = <0x02000000 0 0xe0000000
0297 0x02000000 0 0xe0000000
0298 0 0x20000000
0299
0300 0x01000000 0 0x00000000
0301 0x01000000 0 0x00000000
0302 0 0x00010000>;
0303 };
0304 };
0305
0306 pci1: pcie@ffe250000 {
0307 reg = <0xf 0xfe250000 0 0x10000>;
0308 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0309 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
0310 pcie@0 {
0311 ranges = <0x02000000 0 0xe0000000
0312 0x02000000 0 0xe0000000
0313 0 0x20000000
0314
0315 0x01000000 0 0x00000000
0316 0x01000000 0 0x00000000
0317 0 0x00010000>;
0318 };
0319 };
0320
0321 pci2: pcie@ffe260000 {
0322 reg = <0xf 0xfe260000 0 0x1000>;
0323 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0324 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
0325 pcie@0 {
0326 ranges = <0x02000000 0 0xe0000000
0327 0x02000000 0 0xe0000000
0328 0 0x20000000
0329
0330 0x01000000 0 0x00000000
0331 0x01000000 0 0x00000000
0332 0 0x00010000>;
0333 };
0334 };
0335
0336 pci3: pcie@ffe270000 {
0337 reg = <0xf 0xfe270000 0 0x10000>;
0338 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
0339 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
0340 pcie@0 {
0341 ranges = <0x02000000 0 0xe0000000
0342 0x02000000 0 0xe0000000
0343 0 0x20000000
0344
0345 0x01000000 0 0x00000000
0346 0x01000000 0 0x00000000
0347 0 0x00010000>;
0348 };
0349 };
0350
0351 rio: rapidio@ffe0c0000 {
0352 reg = <0xf 0xfe0c0000 0 0x11000>;
0353
0354 port1 {
0355 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
0356 };
0357 port2 {
0358 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
0359 };
0360 };
0361 };
0362
0363 /include/ "t4240si-post.dtsi"
