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0001 /*
0002 * T4240QDS Device Tree Source
0003 *
0004 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 /include/ "t4240si-pre.dtsi"
0036
0037 / {
0038 model = "fsl,T4240QDS";
0039 compatible = "fsl,T4240QDS";
0040 #address-cells = <2>;
0041 #size-cells = <2>;
0042 interrupt-parent = <&mpic>;
0043
0044 aliases{
0045 phy_rgmii1 = &phyrgmii1;
0046 phy_rgmii2 = &phyrgmii2;
0047 phy_sgmii3 = &phy3;
0048 phy_sgmii4 = &phy4;
0049 phy_sgmii11 = &phy11;
0050 phy_sgmii12 = &phy12;
0051 sgmii_phy11 = &sgmiiphy11;
0052 sgmii_phy12 = &sgmiiphy12;
0053 sgmii_phy13 = &sgmiiphy13;
0054 sgmii_phy14 = &sgmiiphy14;
0055 sgmii_phy21 = &sgmiiphy21;
0056 sgmii_phy22 = &sgmiiphy22;
0057 sgmii_phy23 = &sgmiiphy23;
0058 sgmii_phy24 = &sgmiiphy24;
0059 sgmii_phy31 = &sgmiiphy31;
0060 sgmii_phy32 = &sgmiiphy32;
0061 sgmii_phy33 = &sgmiiphy33;
0062 sgmii_phy34 = &sgmiiphy34;
0063 sgmii_phy41 = &sgmiiphy41;
0064 sgmii_phy42 = &sgmiiphy42;
0065 sgmii_phy43 = &sgmiiphy43;
0066 sgmii_phy44 = &sgmiiphy44;
0067 phy_xfi1 = &xfiphy1;
0068 phy_xfi2 = &xfiphy2;
0069 phy_xfi3 = &xfiphy3;
0070 phy_xfi4 = &xfiphy4;
0071 xfi_pcs_mdio1 = &xfimdio0;
0072 xfi_pcs_mdio2 = &xfimdio1;
0073 xfi_pcs_mdio3 = &xfimdio2;
0074 xfi_pcs_mdio4 = &xfimdio3;
0075 emi1_rgmii = &t4240mdio0;
0076 emi1_slot1 = &t4240mdio1;
0077 emi1_slot2 = &t4240mdio2;
0078 emi1_slot3 = &t4240mdio3;
0079 emi1_slot4 = &t4240mdio4;
0080 };
0081
0082 ifc: localbus@ffe124000 {
0083 reg = <0xf 0xfe124000 0 0x2000>;
0084 ranges = <0 0 0xf 0xe8000000 0x08000000
0085 2 0 0xf 0xff800000 0x00010000
0086 3 0 0xf 0xffdf0000 0x00008000>;
0087
0088 nor@0,0 {
0089 #address-cells = <1>;
0090 #size-cells = <1>;
0091 compatible = "cfi-flash";
0092 reg = <0x0 0x0 0x8000000>;
0093
0094 bank-width = <2>;
0095 device-width = <1>;
0096 };
0097
0098 nand@2,0 {
0099 #address-cells = <1>;
0100 #size-cells = <1>;
0101 compatible = "fsl,ifc-nand";
0102 reg = <0x2 0x0 0x10000>;
0103
0104 partition@0 {
0105 /* This location must not be altered */
0106 /* 1MB for u-boot Bootloader Image */
0107 reg = <0x0 0x00100000>;
0108 label = "NAND U-Boot Image";
0109 read-only;
0110 };
0111
0112 partition@100000 {
0113 /* 1MB for DTB Image */
0114 reg = <0x00100000 0x00100000>;
0115 label = "NAND DTB Image";
0116 };
0117
0118 partition@200000 {
0119 /* 10MB for Linux Kernel Image */
0120 reg = <0x00200000 0x00A00000>;
0121 label = "NAND Linux Kernel Image";
0122 };
0123
0124 partition@C00000 {
0125 /* 500MB for Root file System Image */
0126 reg = <0x00c00000 0x1F400000>;
0127 label = "NAND RFS Image";
0128 };
0129 };
0130
0131 board-control@3,0 {
0132 #address-cells = <1>;
0133 #size-cells = <1>;
0134 compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
0135 reg = <3 0 0x300>;
0136 ranges = <0 3 0 0x300>;
0137
0138 mdio-mux-emi1 {
0139 #address-cells = <1>;
0140 #size-cells = <0>;
0141 compatible = "mdio-mux-mmioreg", "mdio-mux";
0142 mdio-parent-bus = <&mdio1>;
0143 reg = <0x54 1>;
0144 mux-mask = <0xe0>;
0145
0146 t4240mdio0: mdio@0 {
0147 #address-cells = <1>;
0148 #size-cells = <0>;
0149 reg = <0>;
0150
0151 phyrgmii1: ethernet-phy@1 {
0152 reg = <0x1>;
0153 };
0154
0155 phyrgmii2: ethernet-phy@2 {
0156 reg = <0x2>;
0157 };
0158 };
0159
0160 t4240mdio1: mdio@20 {
0161 #address-cells = <1>;
0162 #size-cells = <0>;
0163 reg = <0x20>;
0164 status = "disabled";
0165
0166 phy1: ethernet-phy@0 {
0167 reg = <0x0>;
0168 };
0169
0170 phy2: ethernet-phy@1 {
0171 reg = <0x1>;
0172 };
0173
0174 phy3: ethernet-phy@2 {
0175 reg = <0x2>;
0176 };
0177
0178 phy4: ethernet-phy@3 {
0179 reg = <0x3>;
0180 };
0181
0182 sgmiiphy11: ethernet-phy@1c {
0183 reg = <0x1c>;
0184 };
0185
0186 sgmiiphy12: ethernet-phy@1d {
0187 reg = <0x1d>;
0188 };
0189
0190 sgmiiphy13: ethernet-phy@1e {
0191 reg = <0x1e>;
0192 };
0193
0194 sgmiiphy14: ethernet-phy@1f {
0195 reg = <0x1f>;
0196 };
0197 };
0198
0199 t4240mdio2: mdio@40 {
0200 #address-cells = <1>;
0201 #size-cells = <0>;
0202 reg = <0x40>;
0203 status = "disabled";
0204
0205 phy5: ethernet-phy@4 {
0206 reg = <0x4>;
0207 };
0208
0209 phy6: ethernet-phy@5 {
0210 reg = <0x5>;
0211 };
0212
0213 phy7: ethernet-phy@6 {
0214 reg = <0x6>;
0215 };
0216
0217 phy8: ethernet-phy@7 {
0218 reg = <0x7>;
0219 };
0220
0221 sgmiiphy21: ethernet-phy@1c {
0222 reg = <0x1c>;
0223 };
0224
0225 sgmiiphy22: ethernet-phy@1d {
0226 reg = <0x1d>;
0227 };
0228
0229 sgmiiphy23: ethernet-phy@1e {
0230 reg = <0x1e>;
0231 };
0232
0233 sgmiiphy24: ethernet-phy@1f {
0234 reg = <0x1f>;
0235 };
0236 };
0237
0238 t4240mdio3: mdio@60 {
0239 #address-cells = <1>;
0240 #size-cells = <0>;
0241 reg = <0x60>;
0242 status = "disabled";
0243
0244 phy9: ethernet-phy@8 {
0245 reg = <0x8>;
0246 };
0247
0248 phy10: ethernet-phy@9 {
0249 reg = <0x9>;
0250 };
0251
0252 phy11: ethernet-phy@a {
0253 reg = <0xa>;
0254 };
0255
0256 phy12: ethernet-phy@b {
0257 reg = <0xb>;
0258 };
0259
0260 sgmiiphy31: ethernet-phy@1c {
0261 reg = <0x1c>;
0262 };
0263
0264 sgmiiphy32: ethernet-phy@1d {
0265 reg = <0x1d>;
0266 };
0267
0268 sgmiiphy33: ethernet-phy@1e {
0269 reg = <0x1e>;
0270 };
0271
0272 sgmiiphy34: ethernet-phy@1f {
0273 reg = <0x1f>;
0274 };
0275 };
0276
0277 t4240mdio4: mdio@80 {
0278 #address-cells = <1>;
0279 #size-cells = <0>;
0280 reg = <0x80>;
0281 status = "disabled";
0282
0283 phy13: ethernet-phy@c {
0284 reg = <0xc>;
0285 };
0286
0287 phy14: ethernet-phy@d {
0288 reg = <0xd>;
0289 };
0290
0291 phy15: ethernet-phy@e {
0292 reg = <0xe>;
0293 };
0294
0295 phy16: ethernet-phy@f {
0296 reg = <0xf>;
0297 };
0298
0299 sgmiiphy41: ethernet-phy@1c {
0300 reg = <0x1c>;
0301 };
0302
0303 sgmiiphy42: ethernet-phy@1d {
0304 reg = <0x1d>;
0305 };
0306
0307 sgmiiphy43: ethernet-phy@1e {
0308 reg = <0x1e>;
0309 };
0310
0311 sgmiiphy44: ethernet-phy@1f {
0312 reg = <0x1f>;
0313 };
0314 };
0315 };
0316 };
0317 };
0318
0319 memory {
0320 device_type = "memory";
0321 };
0322
0323 reserved-memory {
0324 #address-cells = <2>;
0325 #size-cells = <2>;
0326 ranges;
0327
0328 bman_fbpr: bman-fbpr {
0329 size = <0 0x1000000>;
0330 alignment = <0 0x1000000>;
0331 };
0332 qman_fqd: qman-fqd {
0333 size = <0 0x400000>;
0334 alignment = <0 0x400000>;
0335 };
0336 qman_pfdr: qman-pfdr {
0337 size = <0 0x2000000>;
0338 alignment = <0 0x2000000>;
0339 };
0340 };
0341
0342 dcsr: dcsr@f00000000 {
0343 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
0344 };
0345
0346 bportals: bman-portals@ff4000000 {
0347 ranges = <0x0 0xf 0xf4000000 0x2000000>;
0348 };
0349
0350 qportals: qman-portals@ff6000000 {
0351 ranges = <0x0 0xf 0xf6000000 0x2000000>;
0352 };
0353
0354 soc: soc@ffe000000 {
0355 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
0356 reg = <0xf 0xfe000000 0 0x00001000>;
0357 spi@110000 {
0358 flash@0 {
0359 #address-cells = <1>;
0360 #size-cells = <1>;
0361 compatible = "sst,sst25wf040", "jedec,spi-nor";
0362 reg = <0>;
0363 spi-max-frequency = <40000000>; /* input clock */
0364 };
0365 };
0366
0367 i2c@118000 {
0368 mux@77 {
0369 compatible = "nxp,pca9547";
0370 reg = <0x77>;
0371 #address-cells = <1>;
0372 #size-cells = <0>;
0373
0374 i2c@0 {
0375 #address-cells = <1>;
0376 #size-cells = <0>;
0377 reg = <0>;
0378
0379 eeprom@51 {
0380 compatible = "atmel,24c256";
0381 reg = <0x51>;
0382 };
0383 eeprom@52 {
0384 compatible = "atmel,24c256";
0385 reg = <0x52>;
0386 };
0387 eeprom@53 {
0388 compatible = "atmel,24c256";
0389 reg = <0x53>;
0390 };
0391 eeprom@54 {
0392 compatible = "atmel,24c256";
0393 reg = <0x54>;
0394 };
0395 eeprom@55 {
0396 compatible = "atmel,24c256";
0397 reg = <0x55>;
0398 };
0399 eeprom@56 {
0400 compatible = "atmel,24c256";
0401 reg = <0x56>;
0402 };
0403 rtc@68 {
0404 compatible = "dallas,ds3232";
0405 reg = <0x68>;
0406 interrupts = <0x1 0x1 0 0>;
0407 };
0408 };
0409
0410 i2c@2 {
0411 #address-cells = <1>;
0412 #size-cells = <0>;
0413 reg = <0x2>;
0414
0415 ina220@40 {
0416 compatible = "ti,ina220";
0417 reg = <0x40>;
0418 shunt-resistor = <1000>;
0419 };
0420
0421 ina220@41 {
0422 compatible = "ti,ina220";
0423 reg = <0x41>;
0424 shunt-resistor = <1000>;
0425 };
0426
0427 ina220@44 {
0428 compatible = "ti,ina220";
0429 reg = <0x44>;
0430 shunt-resistor = <1000>;
0431 };
0432
0433 ina220@45 {
0434 compatible = "ti,ina220";
0435 reg = <0x45>;
0436 shunt-resistor = <1000>;
0437 };
0438
0439 ina220@46 {
0440 compatible = "ti,ina220";
0441 reg = <0x46>;
0442 shunt-resistor = <1000>;
0443 };
0444
0445 ina220@47 {
0446 compatible = "ti,ina220";
0447 reg = <0x47>;
0448 shunt-resistor = <1000>;
0449 };
0450 };
0451 };
0452 };
0453
0454 sdhc@114000 {
0455 voltage-ranges = <1800 1800 3300 3300>;
0456 };
0457
0458 fman@400000 {
0459 port@83000 {
0460 status = "disabled";
0461 };
0462
0463 port@84000 {
0464 status = "disabled";
0465 };
0466
0467 port@85000 {
0468 status = "disabled";
0469 };
0470
0471 port@86000 {
0472 status = "disabled";
0473 };
0474
0475 port@87000 {
0476 status = "disabled";
0477 };
0478
0479 ethernet@e0000 {
0480 phy-handle = <&phy5>;
0481 phy-connection-type = "sgmii";
0482 };
0483
0484 ethernet@e2000 {
0485 phy-handle = <&phy6>;
0486 phy-connection-type = "sgmii";
0487 };
0488
0489 ethernet@e4000 {
0490 phy-handle = <&phy7>;
0491 phy-connection-type = "sgmii";
0492 };
0493
0494 ethernet@e6000 {
0495 phy-handle = <&phy8>;
0496 phy-connection-type = "sgmii";
0497 };
0498
0499 ethernet@e8000 {
0500 phy-handle = <&phyrgmii2>;
0501 phy-connection-type = "rgmii";
0502 };
0503
0504 ethernet@ea000 {
0505 phy-handle = <&phy2>;
0506 phy-connection-type = "sgmii";
0507 };
0508
0509 ethernet@f0000 {
0510 phy-handle = <&xauiphy1>;
0511 phy-connection-type = "xgmii";
0512 };
0513
0514 ethernet@f2000 {
0515 phy-handle = <&xauiphy2>;
0516 phy-connection-type = "xgmii";
0517 };
0518
0519 xfimdio0: mdio@f1000 {
0520 status = "disabled";
0521
0522 xfiphy1: ethernet-phy@0 {
0523 compatible = "ethernet-phy-ieee802.3-c45";
0524 reg = <0x0>;
0525 };
0526 };
0527
0528 xfimdio1: mdio@f3000 {
0529 status = "disabled";
0530
0531 xfiphy2: ethernet-phy@0 {
0532 compatible = "ethernet-phy-ieee802.3-c45";
0533 reg = <0x0>;
0534 };
0535 };
0536 };
0537
0538 fman@500000 {
0539 port@84000 {
0540 status = "disabled";
0541 };
0542
0543 port@85000 {
0544 status = "disabled";
0545 };
0546
0547 port@86000 {
0548 status = "disabled";
0549 };
0550
0551 port@87000 {
0552 status = "disabled";
0553 };
0554
0555 ethernet@e0000 {
0556 phy-handle = <&phy13>;
0557 phy-connection-type = "sgmii";
0558 };
0559
0560 ethernet@e2000 {
0561 phy-handle = <&phy14>;
0562 phy-connection-type = "sgmii";
0563 };
0564
0565 ethernet@e4000 {
0566 phy-handle = <&phy15>;
0567 phy-connection-type = "sgmii";
0568 };
0569
0570 ethernet@e6000 {
0571 phy-handle = <&phy16>;
0572 phy-connection-type = "sgmii";
0573 };
0574
0575 ethernet@e8000 {
0576 phy-handle = <&phyrgmii1>;
0577 phy-connection-type = "rgmii";
0578 };
0579
0580 ethernet@ea000 {
0581 phy-handle = <&phy10>;
0582 phy-connection-type = "sgmii";
0583 };
0584
0585 ethernet@f0000 {
0586 phy-handle = <&xauiphy3>;
0587 phy-connection-type = "xgmii";
0588 };
0589
0590 ethernet@f2000 {
0591 phy-handle = <&xauiphy4>;
0592 phy-connection-type = "xgmii";
0593 };
0594
0595 xfimdio2: mdio@f1000 {
0596 status = "disabled";
0597
0598 xfiphy3: ethernet-phy@0 {
0599 compatible = "ethernet-phy-ieee802.3-c45";
0600 reg = <0x0>;
0601 };
0602 };
0603
0604 xfimdio3: mdio@f3000 {
0605 status = "disabled";
0606
0607 xfiphy4: ethernet-phy@0 {
0608 compatible = "ethernet-phy-ieee802.3-c45";
0609 reg = <0x0>;
0610 };
0611 };
0612
0613 mdio@fd000 {
0614 xauiphy1: ethernet-phy@0 {
0615 compatible = "ethernet-phy-ieee802.3-c45";
0616 reg = <0x0>;
0617 };
0618
0619 xauiphy2: ethernet-phy@1 {
0620 compatible = "ethernet-phy-ieee802.3-c45";
0621 reg = <0x1>;
0622 };
0623
0624 xauiphy3: ethernet-phy@2 {
0625 compatible = "ethernet-phy-ieee802.3-c45";
0626 reg = <0x2>;
0627 };
0628
0629 xauiphy4: ethernet-phy@3 {
0630 compatible = "ethernet-phy-ieee802.3-c45";
0631 reg = <0x3>;
0632 };
0633 };
0634 };
0635 };
0636
0637 pci0: pcie@ffe240000 {
0638 reg = <0xf 0xfe240000 0 0x10000>;
0639 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0640 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
0641 pcie@0 {
0642 ranges = <0x02000000 0 0xe0000000
0643 0x02000000 0 0xe0000000
0644 0 0x20000000
0645
0646 0x01000000 0 0x00000000
0647 0x01000000 0 0x00000000
0648 0 0x00010000>;
0649 };
0650 };
0651
0652 pci1: pcie@ffe250000 {
0653 reg = <0xf 0xfe250000 0 0x10000>;
0654 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0655 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
0656 pcie@0 {
0657 ranges = <0x02000000 0 0xe0000000
0658 0x02000000 0 0xe0000000
0659 0 0x20000000
0660
0661 0x01000000 0 0x00000000
0662 0x01000000 0 0x00000000
0663 0 0x00010000>;
0664 };
0665 };
0666
0667 pci2: pcie@ffe260000 {
0668 reg = <0xf 0xfe260000 0 0x1000>;
0669 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0670 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
0671 pcie@0 {
0672 ranges = <0x02000000 0 0xe0000000
0673 0x02000000 0 0xe0000000
0674 0 0x20000000
0675
0676 0x01000000 0 0x00000000
0677 0x01000000 0 0x00000000
0678 0 0x00010000>;
0679 };
0680 };
0681
0682 pci3: pcie@ffe270000 {
0683 reg = <0xf 0xfe270000 0 0x10000>;
0684 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
0685 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
0686 pcie@0 {
0687 ranges = <0x02000000 0 0xe0000000
0688 0x02000000 0 0xe0000000
0689 0 0x20000000
0690
0691 0x01000000 0 0x00000000
0692 0x01000000 0 0x00000000
0693 0 0x00010000>;
0694 };
0695 };
0696 rio: rapidio@ffe0c0000 {
0697 reg = <0xf 0xfe0c0000 0 0x11000>;
0698
0699 port1 {
0700 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
0701 };
0702 port2 {
0703 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
0704 };
0705 };
0706 };
0707
0708 /include/ "t4240si-post.dtsi"
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