0001 /*
0002 * T2080/T2081 Silicon/SoC Device Tree Source (pre include)
0003 *
0004 * Copyright 2013 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 /dts-v1/;
0036
0037 /include/ "e6500_power_isa.dtsi"
0038
0039 / {
0040 #address-cells = <2>;
0041 #size-cells = <2>;
0042 interrupt-parent = <&mpic>;
0043
0044 aliases {
0045 ccsr = &soc;
0046 dcsr = &dcsr;
0047
0048 serial0 = &serial0;
0049 serial1 = &serial1;
0050 serial2 = &serial2;
0051 serial3 = &serial3;
0052
0053 crypto = &crypto;
0054
0055 fman0 = &fman0;
0056 ethernet0 = &enet0;
0057 ethernet1 = &enet1;
0058 ethernet2 = &enet2;
0059 ethernet3 = &enet3;
0060 ethernet4 = &enet4;
0061 ethernet5 = &enet5;
0062 ethernet6 = &enet6;
0063 ethernet7 = &enet7;
0064
0065 pci0 = &pci0;
0066 pci1 = &pci1;
0067 pci2 = &pci2;
0068 pci3 = &pci3;
0069 usb0 = &usb0;
0070 usb1 = &usb1;
0071 dma0 = &dma0;
0072 dma1 = &dma1;
0073 dma2 = &dma2;
0074 sdhc = &sdhc;
0075 };
0076
0077 cpus {
0078 #address-cells = <1>;
0079 #size-cells = <0>;
0080
0081 cpu0: PowerPC,e6500@0 {
0082 device_type = "cpu";
0083 reg = <0 1>;
0084 clocks = <&clockgen 1 0>;
0085 next-level-cache = <&L2_1>;
0086 fsl,portid-mapping = <0x80000000>;
0087 };
0088 cpu1: PowerPC,e6500@2 {
0089 device_type = "cpu";
0090 reg = <2 3>;
0091 clocks = <&clockgen 1 0>;
0092 next-level-cache = <&L2_1>;
0093 fsl,portid-mapping = <0x80000000>;
0094 };
0095 cpu2: PowerPC,e6500@4 {
0096 device_type = "cpu";
0097 reg = <4 5>;
0098 clocks = <&clockgen 1 0>;
0099 next-level-cache = <&L2_1>;
0100 fsl,portid-mapping = <0x80000000>;
0101 };
0102 cpu3: PowerPC,e6500@6 {
0103 device_type = "cpu";
0104 reg = <6 7>;
0105 clocks = <&clockgen 1 0>;
0106 next-level-cache = <&L2_1>;
0107 fsl,portid-mapping = <0x80000000>;
0108 };
0109 };
0110 };
