0001 /*
0002 * T2080/T2081 QDS Device Tree Source
0003 *
0004 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 / {
0036 model = "fsl,T2080QDS";
0037 compatible = "fsl,T2080QDS";
0038 #address-cells = <2>;
0039 #size-cells = <2>;
0040 interrupt-parent = <&mpic>;
0041
0042 reserved-memory {
0043 #address-cells = <2>;
0044 #size-cells = <2>;
0045 ranges;
0046
0047 bman_fbpr: bman-fbpr {
0048 size = <0 0x1000000>;
0049 alignment = <0 0x1000000>;
0050 };
0051 qman_fqd: qman-fqd {
0052 size = <0 0x400000>;
0053 alignment = <0 0x400000>;
0054 };
0055 qman_pfdr: qman-pfdr {
0056 size = <0 0x2000000>;
0057 alignment = <0 0x2000000>;
0058 };
0059 };
0060
0061 ifc: localbus@ffe124000 {
0062 reg = <0xf 0xfe124000 0 0x2000>;
0063 ranges = <0 0 0xf 0xe8000000 0x08000000
0064 2 0 0xf 0xff800000 0x00010000
0065 3 0 0xf 0xffdf0000 0x00008000>;
0066
0067 nor@0,0 {
0068 #address-cells = <1>;
0069 #size-cells = <1>;
0070 compatible = "cfi-flash";
0071 reg = <0x0 0x0 0x8000000>;
0072 bank-width = <2>;
0073 device-width = <1>;
0074 };
0075
0076 nand@2,0 {
0077 #address-cells = <1>;
0078 #size-cells = <1>;
0079 compatible = "fsl,ifc-nand";
0080 reg = <0x2 0x0 0x10000>;
0081 };
0082
0083 boardctrl: board-control@3,0 {
0084 #address-cells = <1>;
0085 #size-cells = <1>;
0086 compatible = "fsl,fpga-qixis";
0087 reg = <3 0 0x300>;
0088 ranges = <0 3 0 0x300>;
0089 };
0090 };
0091
0092 memory {
0093 device_type = "memory";
0094 };
0095
0096 dcsr: dcsr@f00000000 {
0097 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
0098 };
0099
0100 bportals: bman-portals@ff4000000 {
0101 ranges = <0x0 0xf 0xf4000000 0x2000000>;
0102 };
0103
0104 qportals: qman-portals@ff6000000 {
0105 ranges = <0x0 0xf 0xf6000000 0x2000000>;
0106 };
0107
0108 soc: soc@ffe000000 {
0109 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
0110 reg = <0xf 0xfe000000 0 0x00001000>;
0111 spi@110000 {
0112 flash@0 {
0113 #address-cells = <1>;
0114 #size-cells = <1>;
0115 compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
0116 reg = <0>;
0117 spi-max-frequency = <40000000>; /* input clock */
0118 };
0119
0120 flash@1 {
0121 #address-cells = <1>;
0122 #size-cells = <1>;
0123 compatible = "sst,sst25wf040", "jedec,spi-nor";
0124 reg = <1>;
0125 spi-max-frequency = <35000000>;
0126 };
0127
0128 flash@2 {
0129 #address-cells = <1>;
0130 #size-cells = <1>;
0131 compatible = "eon,en25s64", "jedec,spi-nor";
0132 reg = <2>;
0133 spi-max-frequency = <35000000>;
0134 };
0135 };
0136
0137 i2c@118000 {
0138 pca9547@77 {
0139 compatible = "nxp,pca9547";
0140 reg = <0x77>;
0141 #address-cells = <1>;
0142 #size-cells = <0>;
0143
0144 i2c@0 {
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147 reg = <0x0>;
0148
0149 eeprom@50 {
0150 compatible = "atmel,24c512";
0151 reg = <0x50>;
0152 };
0153
0154 eeprom@51 {
0155 compatible = "atmel,24c02";
0156 reg = <0x51>;
0157 };
0158
0159 eeprom@57 {
0160 compatible = "atmel,24c02";
0161 reg = <0x57>;
0162 };
0163
0164 rtc@68 {
0165 compatible = "dallas,ds3232";
0166 reg = <0x68>;
0167 interrupts = <0xb 0x1 0 0>;
0168 };
0169 };
0170
0171 i2c@1 {
0172 #address-cells = <1>;
0173 #size-cells = <0>;
0174 reg = <0x1>;
0175
0176 eeprom@55 {
0177 compatible = "atmel,24c02";
0178 reg = <0x55>;
0179 };
0180 };
0181
0182 i2c@2 {
0183 #address-cells = <1>;
0184 #size-cells = <0>;
0185 reg = <0x2>;
0186
0187 ina220@40 {
0188 compatible = "ti,ina220";
0189 reg = <0x40>;
0190 shunt-resistor = <1000>;
0191 };
0192
0193 ina220@41 {
0194 compatible = "ti,ina220";
0195 reg = <0x41>;
0196 shunt-resistor = <1000>;
0197 };
0198 };
0199
0200 i2c@3 {
0201 #address-cells = <1>;
0202 #size-cells = <0>;
0203 reg = <0x3>;
0204
0205 adt7461@4c {
0206 compatible = "adi,adt7461";
0207 reg = <0x4c>;
0208 };
0209 };
0210 };
0211 };
0212
0213 sdhc@114000 {
0214 voltage-ranges = <1800 1800 3300 3300>;
0215 };
0216 };
0217
0218 pci0: pcie@ffe240000 {
0219 reg = <0xf 0xfe240000 0 0x10000>;
0220 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0221 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
0222 pcie@0 {
0223 ranges = <0x02000000 0 0xe0000000
0224 0x02000000 0 0xe0000000
0225 0 0x20000000
0226
0227 0x01000000 0 0x00000000
0228 0x01000000 0 0x00000000
0229 0 0x00010000>;
0230 };
0231 };
0232
0233 pci1: pcie@ffe250000 {
0234 reg = <0xf 0xfe250000 0 0x10000>;
0235 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000
0236 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
0237 pcie@0 {
0238 ranges = <0x02000000 0 0xe0000000
0239 0x02000000 0 0xe0000000
0240 0 0x20000000
0241
0242 0x01000000 0 0x00000000
0243 0x01000000 0 0x00000000
0244 0 0x00010000>;
0245 };
0246 };
0247
0248 pci2: pcie@ffe260000 {
0249 reg = <0xf 0xfe260000 0 0x1000>;
0250 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
0251 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
0252 pcie@0 {
0253 ranges = <0x02000000 0 0xe0000000
0254 0x02000000 0 0xe0000000
0255 0 0x20000000
0256
0257 0x01000000 0 0x00000000
0258 0x01000000 0 0x00000000
0259 0 0x00010000>;
0260 };
0261 };
0262
0263 pci3: pcie@ffe270000 {
0264 reg = <0xf 0xfe270000 0 0x10000>;
0265 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000
0266 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
0267 pcie@0 {
0268 ranges = <0x02000000 0 0xe0000000
0269 0x02000000 0 0xe0000000
0270 0 0x20000000
0271
0272 0x01000000 0 0x00000000
0273 0x01000000 0 0x00000000
0274 0 0x00010000>;
0275 };
0276 };
0277 };
