0001 /*
0002 * T2081QDS Device Tree Source
0003 *
0004 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 /include/ "t208xsi-pre.dtsi"
0036 /include/ "t208xqds.dtsi"
0037
0038 / {
0039 model = "fsl,T2081QDS";
0040 compatible = "fsl,T2081QDS";
0041 #address-cells = <2>;
0042 #size-cells = <2>;
0043 interrupt-parent = <&mpic>;
0044
0045 aliases {
0046 emi1_slot1 = &t2081mdio2;
0047 emi1_slot2 = &t2081mdio3;
0048 emi1_slot3 = &t2081mdio4;
0049 emi1_slot5 = &t2081mdio5;
0050 emi1_slot6 = &t2081mdio6;
0051 emi1_slot7 = &t2081mdio7;
0052 };
0053 };
0054
0055 &soc {
0056 fman@400000 {
0057 ethernet@e0000 {
0058 phy-handle = <&phy_sgmii_s7_1c>;
0059 phy-connection-type = "sgmii";
0060 };
0061
0062 ethernet@e2000 {
0063 phy-handle = <&phy_sgmii_s7_1d>;
0064 phy-connection-type = "sgmii";
0065 };
0066
0067 ethernet@e4000 {
0068 phy-handle = <&rgmii_phy1>;
0069 phy-connection-type = "rgmii";
0070 };
0071
0072 ethernet@e6000 {
0073 phy-handle = <&rgmii_phy2>;
0074 phy-connection-type = "rgmii";
0075 };
0076
0077 ethernet@e8000 {
0078 phy-handle = <&phy_sgmii_s3_1c>;
0079 phy-connection-type = "sgmii";
0080 };
0081
0082 ethernet@ea000 {
0083 phy-handle = <&phy_sgmii_s7_1f>;
0084 phy-connection-type = "sgmii";
0085 };
0086
0087 ethernet@f0000 {
0088 phy-handle = <&phy_sgmii_s2_1c>;
0089 phy-connection-type = "xgmii";
0090 };
0091
0092 ethernet@f2000 {
0093 phy-handle = <&phy_sgmii_s7_1e>;
0094 phy-connection-type = "xgmii";
0095 };
0096 };
0097 };
0098
0099 &boardctrl {
0100 mdio-mux-emi1 {
0101 compatible = "mdio-mux-mmioreg", "mdio-mux";
0102 mdio-parent-bus = <&mdio0>;
0103 #address-cells = <1>;
0104 #size-cells = <0>;
0105 reg = <0x54 1>;
0106 mux-mask = <0xe0>;
0107
0108 t2081mdio0: mdio@0 {
0109 #address-cells = <1>;
0110 #size-cells = <0>;
0111 reg = <0>;
0112
0113 rgmii_phy1: ethernet-phy@1 {
0114 reg = <0x1>;
0115 };
0116 };
0117
0118 t2081mdio1: mdio@20 {
0119 #address-cells = <1>;
0120 #size-cells = <0>;
0121 reg = <0x20>;
0122
0123 rgmii_phy2: ethernet-phy@2 {
0124 reg = <0x2>;
0125 };
0126 };
0127
0128 t2081mdio2: mdio@40 {
0129 #address-cells = <1>;
0130 #size-cells = <0>;
0131 reg = <0x40>;
0132
0133 phy_sgmii_s1_1c: ethernet-phy@1c {
0134 reg = <0x1c>;
0135 };
0136
0137 phy_sgmii_s1_1d: ethernet-phy@1d {
0138 reg = <0x1d>;
0139 };
0140
0141 phy_sgmii_s1_1e: ethernet-phy@1e {
0142 reg = <0x1e>;
0143 };
0144
0145 phy_sgmii_s1_1f: ethernet-phy@1f {
0146 reg = <0x1f>;
0147 };
0148 };
0149
0150 t2081mdio3: mdio@60 {
0151 #address-cells = <1>;
0152 #size-cells = <0>;
0153 reg = <0x60>;
0154
0155 phy_sgmii_s2_1c: ethernet-phy@1c {
0156 reg = <0x1c>;
0157 };
0158
0159 phy_sgmii_s2_1d: ethernet-phy@1d {
0160 reg = <0x1d>;
0161 };
0162
0163 phy_sgmii_s2_1e: ethernet-phy@1e {
0164 reg = <0x1e>;
0165 };
0166
0167 phy_sgmii_s2_1f: ethernet-phy@1f {
0168 reg = <0x1f>;
0169 };
0170 };
0171
0172 t2081mdio4: mdio@80 {
0173 #address-cells = <1>;
0174 #size-cells = <0>;
0175 reg = <0x80>;
0176 status = "disabled";
0177
0178 phy_sgmii_s3_1c: ethernet-phy@1c {
0179 reg = <0x1c>;
0180 };
0181
0182 phy_sgmii_s3_1d: ethernet-phy@1d {
0183 reg = <0x1d>;
0184 };
0185
0186 phy_sgmii_s3_1e: ethernet-phy@1e {
0187 reg = <0x1e>;
0188 };
0189
0190 phy_sgmii_s3_1f: ethernet-phy@1f {
0191 reg = <0x1f>;
0192 };
0193 };
0194
0195 t2081mdio5: mdio@a0 {
0196 #address-cells = <1>;
0197 #size-cells = <0>;
0198 reg = <0xa0>;
0199 status = "disabled";
0200
0201 phy_sgmii_s5_1c: ethernet-phy@1c {
0202 reg = <0x1c>;
0203 };
0204
0205 phy_sgmii_s5_1d: ethernet-phy@1d {
0206 reg = <0x1d>;
0207 };
0208
0209 phy_sgmii_s5_1e: ethernet-phy@1e {
0210 reg = <0x1e>;
0211 };
0212
0213 phy_sgmii_s5_1f: ethernet-phy@1f {
0214 reg = <0x1f>;
0215 };
0216 };
0217
0218 t2081mdio6: mdio@c0 {
0219 #address-cells = <1>;
0220 #size-cells = <0>;
0221 reg = <0xc0>;
0222 status = "disabled";
0223
0224 phy_sgmii_s6_1c: ethernet-phy@1c {
0225 reg = <0x1c>;
0226 };
0227
0228 phy_sgmii_s6_1d: ethernet-phy@1d {
0229 reg = <0x1d>;
0230 };
0231
0232 phy_sgmii_s6_1e: ethernet-phy@1e {
0233 reg = <0x1e>;
0234 };
0235
0236 phy_sgmii_s6_1f: ethernet-phy@1f {
0237 reg = <0x1f>;
0238 };
0239 };
0240
0241 t2081mdio7: mdio@e0 {
0242 #address-cells = <1>;
0243 #size-cells = <0>;
0244 reg = <0xe0>;
0245
0246 phy_sgmii_s7_1c: ethernet-phy@1c {
0247 reg = <0x1c>;
0248 };
0249
0250 phy_sgmii_s7_1d: ethernet-phy@1d {
0251 reg = <0x1d>;
0252 };
0253
0254 phy_sgmii_s7_1e: ethernet-phy@1e {
0255 reg = <0x1e>;
0256 };
0257
0258 phy_sgmii_s7_1f: ethernet-phy@1f {
0259 reg = <0x1f>;
0260 };
0261 };
0262 };
0263 };
0264
0265 /include/ "t2081si-post.dtsi"
