0001 /*
0002 * T1040RDB/T1042RDB Device Tree Source
0003 *
0004 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 / {
0036 aliases {
0037 phy_rgmii_0 = &phy_rgmii_0;
0038 phy_rgmii_1 = &phy_rgmii_1;
0039 phy_sgmii_2 = &phy_sgmii_2;
0040 };
0041
0042 reserved-memory {
0043 #address-cells = <2>;
0044 #size-cells = <2>;
0045 ranges;
0046
0047 bman_fbpr: bman-fbpr {
0048 size = <0 0x1000000>;
0049 alignment = <0 0x1000000>;
0050 };
0051 qman_fqd: qman-fqd {
0052 size = <0 0x400000>;
0053 alignment = <0 0x400000>;
0054 };
0055 qman_pfdr: qman-pfdr {
0056 size = <0 0x2000000>;
0057 alignment = <0 0x2000000>;
0058 };
0059 };
0060
0061 ifc: localbus@ffe124000 {
0062 reg = <0xf 0xfe124000 0 0x2000>;
0063 ranges = <0 0 0xf 0xe8000000 0x08000000
0064 2 0 0xf 0xff800000 0x00010000
0065 3 0 0xf 0xffdf0000 0x00008000>;
0066
0067 nor@0,0 {
0068 #address-cells = <1>;
0069 #size-cells = <1>;
0070 compatible = "cfi-flash";
0071 reg = <0x0 0x0 0x8000000>;
0072 bank-width = <2>;
0073 device-width = <1>;
0074 };
0075
0076 nand@2,0 {
0077 #address-cells = <1>;
0078 #size-cells = <1>;
0079 compatible = "fsl,ifc-nand";
0080 reg = <0x2 0x0 0x10000>;
0081 };
0082
0083 cpld@3,0 {
0084 reg = <3 0 0x300>;
0085 };
0086 };
0087
0088 memory {
0089 device_type = "memory";
0090 };
0091
0092 dcsr: dcsr@f00000000 {
0093 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
0094 };
0095
0096 bportals: bman-portals@ff4000000 {
0097 ranges = <0x0 0xf 0xf4000000 0x2000000>;
0098 };
0099
0100 qportals: qman-portals@ff6000000 {
0101 ranges = <0x0 0xf 0xf6000000 0x2000000>;
0102 };
0103
0104 soc: soc@ffe000000 {
0105 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
0106 reg = <0xf 0xfe000000 0 0x00001000>;
0107
0108 spi@110000 {
0109 flash@0 {
0110 #address-cells = <1>;
0111 #size-cells = <1>;
0112 compatible = "micron,n25q512ax3", "jedec,spi-nor";
0113 reg = <0>;
0114 spi-max-frequency = <10000000>; /* input clock */
0115 };
0116 slic@3 {
0117 compatible = "maxim,ds26522";
0118 reg = <3>;
0119 spi-max-frequency = <2000000>; /* input clock */
0120 };
0121 };
0122
0123 i2c@118000 {
0124 adt7461@4c {
0125 compatible = "adi,adt7461";
0126 reg = <0x4c>;
0127 };
0128 };
0129
0130 i2c@118100 {
0131 pca9546@77 {
0132 compatible = "nxp,pca9546";
0133 reg = <0x77>;
0134 #address-cells = <1>;
0135 #size-cells = <0>;
0136 };
0137 };
0138
0139 fman@400000 {
0140 ethernet@e6000 {
0141 phy-handle = <&phy_rgmii_0>;
0142 phy-connection-type = "rgmii-id";
0143 };
0144
0145 ethernet@e8000 {
0146 phy-handle = <&phy_rgmii_1>;
0147 phy-connection-type = "rgmii-id";
0148 };
0149
0150 mdio0: mdio@fc000 {
0151 phy_sgmii_2: ethernet-phy@3 {
0152 reg = <0x03>;
0153 };
0154
0155 phy_rgmii_0: ethernet-phy@1 {
0156 reg = <0x01>;
0157 };
0158
0159 phy_rgmii_1: ethernet-phy@2 {
0160 reg = <0x02>;
0161 };
0162 };
0163 };
0164 };
0165
0166 pci0: pcie@ffe240000 {
0167 reg = <0xf 0xfe240000 0 0x10000>;
0168 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
0169 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
0170 pcie@0 {
0171 ranges = <0x02000000 0 0xe0000000
0172 0x02000000 0 0xe0000000
0173 0 0x10000000
0174
0175 0x01000000 0 0x00000000
0176 0x01000000 0 0x00000000
0177 0 0x00010000>;
0178 };
0179 };
0180
0181 pci1: pcie@ffe250000 {
0182 reg = <0xf 0xfe250000 0 0x10000>;
0183 ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
0184 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
0185 pcie@0 {
0186 ranges = <0x02000000 0 0xe0000000
0187 0x02000000 0 0xe0000000
0188 0 0x10000000
0189
0190 0x01000000 0 0x00000000
0191 0x01000000 0 0x00000000
0192 0 0x00010000>;
0193 };
0194 };
0195
0196 pci2: pcie@ffe260000 {
0197 reg = <0xf 0xfe260000 0 0x10000>;
0198 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
0199 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
0200 pcie@0 {
0201 ranges = <0x02000000 0 0xe0000000
0202 0x02000000 0 0xe0000000
0203 0 0x10000000
0204
0205 0x01000000 0 0x00000000
0206 0x01000000 0 0x00000000
0207 0 0x00010000>;
0208 };
0209 };
0210
0211 pci3: pcie@ffe270000 {
0212 reg = <0xf 0xfe270000 0 0x10000>;
0213 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
0214 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
0215 pcie@0 {
0216 ranges = <0x02000000 0 0xe0000000
0217 0x02000000 0 0xe0000000
0218 0 0x10000000
0219
0220 0x01000000 0 0x00000000
0221 0x01000000 0 0x00000000
0222 0 0x00010000>;
0223 };
0224 };
0225
0226 qe: qe@ffe140000 {
0227 ranges = <0x0 0xf 0xfe140000 0x40000>;
0228 reg = <0xf 0xfe140000 0 0x480>;
0229 brg-frequency = <0>;
0230 bus-frequency = <0>;
0231
0232 si1: si@700 {
0233 compatible = "fsl,t1040-qe-si";
0234 reg = <0x700 0x80>;
0235 };
0236
0237 siram1: siram@1000 {
0238 compatible = "fsl,t1040-qe-siram";
0239 reg = <0x1000 0x800>;
0240 };
0241
0242 ucc_hdlc: ucc@2000 {
0243 compatible = "fsl,ucc-hdlc";
0244 rx-clock-name = "clk8";
0245 tx-clock-name = "clk9";
0246 fsl,rx-sync-clock = "rsync_pin";
0247 fsl,tx-sync-clock = "tsync_pin";
0248 fsl,tx-timeslot-mask = <0xfffffffe>;
0249 fsl,rx-timeslot-mask = <0xfffffffe>;
0250 fsl,tdm-framer-type = "e1";
0251 fsl,tdm-id = <0>;
0252 fsl,siram-entry-id = <0>;
0253 fsl,tdm-interface;
0254 };
0255
0256 ucc_serial: ucc@2200 {
0257 compatible = "fsl,t1040-ucc-uart";
0258 port-number = <0>;
0259 rx-clock-name = "brg2";
0260 tx-clock-name = "brg2";
0261 };
0262 };
0263 };
