0001 /*
0002 * T104xQDS Device Tree Source
0003 *
0004 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 / {
0036 model = "fsl,T1040QDS";
0037 #address-cells = <2>;
0038 #size-cells = <2>;
0039 interrupt-parent = <&mpic>;
0040
0041 aliases {
0042 emi1_rgmii0 = &t1040mdio0;
0043 emi1_rgmii1 = &t1040mdio1;
0044 emi1_slot3 = &t1040mdio3;
0045 emi1_slot5 = &t1040mdio5;
0046 emi1_slot6 = &t1040mdio6;
0047 emi1_slot7 = &t1040mdio7;
0048 rgmii_phy1 = &rgmii_phy1;
0049 rgmii_phy2 = &rgmii_phy2;
0050 phy_s3_01 = &phy_s3_01;
0051 phy_s3_02 = &phy_s3_02;
0052 phy_s3_03 = &phy_s3_03;
0053 phy_s3_04 = &phy_s3_04;
0054 phy_s5_01 = &phy_s5_01;
0055 phy_s5_02 = &phy_s5_02;
0056 phy_s5_03 = &phy_s5_03;
0057 phy_s5_04 = &phy_s5_04;
0058 phy_s6_01 = &phy_s6_01;
0059 phy_s6_02 = &phy_s6_02;
0060 phy_s6_03 = &phy_s6_03;
0061 phy_s6_04 = &phy_s6_04;
0062 phy_s7_01 = &phy_s7_01;
0063 phy_s7_02 = &phy_s7_02;
0064 phy_s7_03 = &phy_s7_03;
0065 phy_s7_04 = &phy_s7_04;
0066 };
0067
0068 reserved-memory {
0069 #address-cells = <2>;
0070 #size-cells = <2>;
0071 ranges;
0072
0073 bman_fbpr: bman-fbpr {
0074 size = <0 0x1000000>;
0075 alignment = <0 0x1000000>;
0076 };
0077 qman_fqd: qman-fqd {
0078 size = <0 0x400000>;
0079 alignment = <0 0x400000>;
0080 };
0081 qman_pfdr: qman-pfdr {
0082 size = <0 0x2000000>;
0083 alignment = <0 0x2000000>;
0084 };
0085 };
0086
0087 ifc: localbus@ffe124000 {
0088 reg = <0xf 0xfe124000 0 0x2000>;
0089 ranges = <0 0 0xf 0xe8000000 0x08000000
0090 2 0 0xf 0xff800000 0x00010000
0091 3 0 0xf 0xffdf0000 0x00008000>;
0092
0093 nor@0,0 {
0094 #address-cells = <1>;
0095 #size-cells = <1>;
0096 compatible = "cfi-flash";
0097 reg = <0x0 0x0 0x8000000>;
0098
0099 bank-width = <2>;
0100 device-width = <1>;
0101 };
0102
0103 nand@2,0 {
0104 #address-cells = <1>;
0105 #size-cells = <1>;
0106 compatible = "fsl,ifc-nand";
0107 reg = <0x2 0x0 0x10000>;
0108 };
0109
0110 board-control@3,0 {
0111 #address-cells = <1>;
0112 #size-cells = <1>;
0113 compatible = "fsl,fpga-qixis";
0114 reg = <3 0 0x300>;
0115 ranges = <0 3 0 0x300>;
0116
0117 mdio-mux-emi1 {
0118 #address-cells = <1>;
0119 #size-cells = <0>;
0120 compatible = "mdio-mux-mmioreg", "mdio-mux";
0121 mdio-parent-bus = <&mdio0>;
0122 reg = <0x54 1>;
0123 mux-mask = <0xe0>;
0124
0125 t1040mdio0: mdio@0 {
0126 #address-cells = <1>;
0127 #size-cells = <0>;
0128 reg = <0x00>;
0129 status = "disabled";
0130
0131 rgmii_phy1: ethernet-phy@1 {
0132 reg = <0x1>;
0133 };
0134 };
0135
0136 t1040mdio1: mdio@20 {
0137 #address-cells = <1>;
0138 #size-cells = <0>;
0139 reg = <0x20>;
0140 status = "disabled";
0141
0142 rgmii_phy2: ethernet-phy@2 {
0143 reg = <0x2>;
0144 };
0145 };
0146
0147 t1040mdio3: mdio@60 {
0148 #address-cells = <1>;
0149 #size-cells = <0>;
0150 reg = <0x60>;
0151 status = "disabled";
0152
0153 phy_s3_01: ethernet-phy@1c {
0154 reg = <0x1c>;
0155 };
0156
0157 phy_s3_02: ethernet-phy@1d {
0158 reg = <0x1d>;
0159 };
0160
0161 phy_s3_03: ethernet-phy@1e {
0162 reg = <0x1e>;
0163 };
0164
0165 phy_s3_04: ethernet-phy@1f {
0166 reg = <0x1f>;
0167 };
0168 };
0169
0170 t1040mdio5: mdio@a0 {
0171 #address-cells = <1>;
0172 #size-cells = <0>;
0173 reg = <0xa0>;
0174
0175 phy_s5_01: ethernet-phy@1c {
0176 reg = <0x14>;
0177 };
0178
0179 phy_s5_02: ethernet-phy@1d {
0180 reg = <0x15>;
0181 };
0182
0183 phy_s5_03: ethernet-phy@1e {
0184 reg = <0x16>;
0185 };
0186
0187 phy_s5_04: ethernet-phy@1f {
0188 reg = <0x17>;
0189 };
0190 };
0191
0192 t1040mdio6: mdio@c0 {
0193 #address-cells = <1>;
0194 #size-cells = <0>;
0195 reg = <0xc0>;
0196
0197 phy_s6_01: ethernet-phy@1c {
0198 reg = <0x18>;
0199 };
0200
0201 phy_s6_02: ethernet-phy@1d {
0202 reg = <0x19>;
0203 };
0204
0205 phy_s6_03: ethernet-phy@1e {
0206 reg = <0x1a>;
0207 };
0208
0209 phy_s6_04: ethernet-phy@1f {
0210 reg = <0x1b>;
0211 };
0212 };
0213
0214 t1040mdio7: mdio@e0 {
0215 #address-cells = <1>;
0216 #size-cells = <0>;
0217 reg = <0xe0>;
0218 status = "disabled";
0219
0220 phy_s7_01: ethernet-phy@1c {
0221 reg = <0x1c>;
0222 };
0223
0224 phy_s7_02: ethernet-phy@1d {
0225 reg = <0x1d>;
0226 };
0227
0228 phy_s7_03: ethernet-phy@1e {
0229 reg = <0x1e>;
0230 };
0231
0232 phy_s7_04: ethernet-phy@1f {
0233 reg = <0x1f>;
0234 };
0235 };
0236 };
0237 };
0238 };
0239
0240 memory {
0241 device_type = "memory";
0242 };
0243
0244 dcsr: dcsr@f00000000 {
0245 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
0246 };
0247
0248 bportals: bman-portals@ff4000000 {
0249 ranges = <0x0 0xf 0xf4000000 0x2000000>;
0250 };
0251
0252 qportals: qman-portals@ff6000000 {
0253 ranges = <0x0 0xf 0xf6000000 0x2000000>;
0254 };
0255
0256 soc: soc@ffe000000 {
0257 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
0258 reg = <0xf 0xfe000000 0 0x00001000>;
0259
0260 spi@110000 {
0261 flash@0 {
0262 #address-cells = <1>;
0263 #size-cells = <1>;
0264 compatible = "micron,n25q128a11", "jedec,spi-nor";
0265 reg = <0>;
0266 spi-max-frequency = <10000000>; /* input clock */
0267 };
0268 };
0269
0270 i2c@118000 {
0271 pca9547@77 {
0272 compatible = "nxp,pca9547";
0273 reg = <0x77>;
0274 };
0275 rtc@68 {
0276 compatible = "dallas,ds3232";
0277 reg = <0x68>;
0278 interrupts = <0x1 0x1 0 0>;
0279 };
0280 };
0281
0282 fman@400000 {
0283 ethernet@e0000 {
0284 fixed-link = <0 1 1000 0 0>;
0285 phy-connection-type = "sgmii";
0286 };
0287
0288 ethernet@e2000 {
0289 fixed-link = <1 1 1000 0 0>;
0290 phy-connection-type = "sgmii";
0291 };
0292
0293 ethernet@e4000 {
0294 phy-handle = <&phy_s7_03>;
0295 phy-connection-type = "sgmii";
0296 };
0297
0298 ethernet@e6000 {
0299 phy-handle = <&rgmii_phy1>;
0300 phy-connection-type = "rgmii";
0301 };
0302
0303 ethernet@e8000 {
0304 phy-handle = <&rgmii_phy2>;
0305 phy-connection-type = "rgmii";
0306 };
0307 };
0308 };
0309
0310 pci0: pcie@ffe240000 {
0311 reg = <0xf 0xfe240000 0 0x10000>;
0312 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
0313 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
0314 pcie@0 {
0315 ranges = <0x02000000 0 0xe0000000
0316 0x02000000 0 0xe0000000
0317 0 0x10000000
0318
0319 0x01000000 0 0x00000000
0320 0x01000000 0 0x00000000
0321 0 0x00010000>;
0322 };
0323 };
0324
0325 pci1: pcie@ffe250000 {
0326 reg = <0xf 0xfe250000 0 0x10000>;
0327 ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
0328 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
0329 pcie@0 {
0330 ranges = <0x02000000 0 0xe0000000
0331 0x02000000 0 0xe0000000
0332 0 0x10000000
0333
0334 0x01000000 0 0x00000000
0335 0x01000000 0 0x00000000
0336 0 0x00010000>;
0337 };
0338 };
0339
0340 pci2: pcie@ffe260000 {
0341 reg = <0xf 0xfe260000 0 0x10000>;
0342 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
0343 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
0344 pcie@0 {
0345 ranges = <0x02000000 0 0xe0000000
0346 0x02000000 0 0xe0000000
0347 0 0x10000000
0348
0349 0x01000000 0 0x00000000
0350 0x01000000 0 0x00000000
0351 0 0x00010000>;
0352 };
0353 };
0354
0355 pci3: pcie@ffe270000 {
0356 reg = <0xf 0xfe270000 0 0x10000>;
0357 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
0358 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
0359 pcie@0 {
0360 ranges = <0x02000000 0 0xe0000000
0361 0x02000000 0 0xe0000000
0362 0 0x10000000
0363
0364 0x01000000 0 0x00000000
0365 0x01000000 0 0x00000000
0366 0 0x00010000>;
0367 };
0368 };
0369
0370 qe: qe@ffe140000 {
0371 ranges = <0x0 0xf 0xfe140000 0x40000>;
0372 reg = <0xf 0xfe140000 0 0x480>;
0373 brg-frequency = <0>;
0374 bus-frequency = <0>;
0375
0376 si1: si@700 {
0377 compatible = "fsl,t1040-qe-si";
0378 reg = <0x700 0x80>;
0379 };
0380
0381 siram1: siram@1000 {
0382 compatible = "fsl,t1040-qe-siram";
0383 reg = <0x1000 0x800>;
0384 };
0385
0386 ucc_hdlc: ucc@2000 {
0387 compatible = "fsl,ucc-hdlc";
0388 rx-clock-name = "clk8";
0389 tx-clock-name = "clk9";
0390 fsl,rx-sync-clock = "rsync_pin";
0391 fsl,tx-sync-clock = "tsync_pin";
0392 fsl,tx-timeslot-mask = <0xfffffffe>;
0393 fsl,rx-timeslot-mask = <0xfffffffe>;
0394 fsl,tdm-framer-type = "e1";
0395 fsl,tdm-id = <0>;
0396 fsl,siram-entry-id = <0>;
0397 fsl,tdm-interface;
0398 };
0399
0400 ucc_serial: ucc@2200 {
0401 compatible = "fsl,t1040-ucc-uart";
0402 port-number = <0>;
0403 rx-clock-name = "brg2";
0404 tx-clock-name = "brg2";
0405 };
0406 };
0407 };
