0001 /*
0002 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
0003 *
0004 * Copyright 2013 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 mpic: pic@40000 {
0036 interrupt-controller;
0037 #address-cells = <0>;
0038 #interrupt-cells = <4>;
0039 reg = <0x40000 0x40000>;
0040 compatible = "fsl,mpic";
0041 device_type = "open-pic";
0042 clock-frequency = <0x0>;
0043 };
0044
0045 timer@41100 {
0046 compatible = "fsl,mpic-global-timer";
0047 reg = <0x41100 0x100 0x41300 4>;
0048 interrupts = <0 0 3 0
0049 1 0 3 0
0050 2 0 3 0
0051 3 0 3 0>;
0052 };
0053
0054 msi0: msi@41600 {
0055 compatible = "fsl,mpic-msi-v4.3";
0056 reg = <0x41600 0x200 0x44148 4>;
0057 interrupts = <
0058 0xe0 0 0 0
0059 0xe1 0 0 0
0060 0xe2 0 0 0
0061 0xe3 0 0 0
0062 0xe4 0 0 0
0063 0xe5 0 0 0
0064 0xe6 0 0 0
0065 0xe7 0 0 0
0066 0x100 0 0 0
0067 0x101 0 0 0
0068 0x102 0 0 0
0069 0x103 0 0 0
0070 0x104 0 0 0
0071 0x105 0 0 0
0072 0x106 0 0 0
0073 0x107 0 0 0>;
0074 };
0075
0076 msi1: msi@41800 {
0077 compatible = "fsl,mpic-msi-v4.3";
0078 reg = <0x41800 0x200 0x45148 4>;
0079 interrupts = <
0080 0xe8 0 0 0
0081 0xe9 0 0 0
0082 0xea 0 0 0
0083 0xeb 0 0 0
0084 0xec 0 0 0
0085 0xed 0 0 0
0086 0xee 0 0 0
0087 0xef 0 0 0
0088 0x108 0 0 0
0089 0x109 0 0 0
0090 0x10a 0 0 0
0091 0x10b 0 0 0
0092 0x10c 0 0 0
0093 0x10d 0 0 0
0094 0x10e 0 0 0
0095 0x10f 0 0 0>;
0096 };
0097
0098 msi2: msi@41a00 {
0099 compatible = "fsl,mpic-msi-v4.3";
0100 reg = <0x41a00 0x200 0x46148 4>;
0101 interrupts = <
0102 0xf0 0 0 0
0103 0xf1 0 0 0
0104 0xf2 0 0 0
0105 0xf3 0 0 0
0106 0xf4 0 0 0
0107 0xf5 0 0 0
0108 0xf6 0 0 0
0109 0xf7 0 0 0
0110 0x110 0 0 0
0111 0x111 0 0 0
0112 0x112 0 0 0
0113 0x113 0 0 0
0114 0x114 0 0 0
0115 0x115 0 0 0
0116 0x116 0 0 0
0117 0x117 0 0 0>;
0118 };
0119
0120 msi3: msi@41c00 {
0121 compatible = "fsl,mpic-msi-v4.3";
0122 reg = <0x41c00 0x200 0x47148 4>;
0123 interrupts = <
0124 0xf8 0 0 0
0125 0xf9 0 0 0
0126 0xfa 0 0 0
0127 0xfb 0 0 0
0128 0xfc 0 0 0
0129 0xfd 0 0 0
0130 0xfe 0 0 0
0131 0xff 0 0 0
0132 0x118 0 0 0
0133 0x119 0 0 0
0134 0x11a 0 0 0
0135 0x11b 0 0 0
0136 0x11c 0 0 0
0137 0x11d 0 0 0
0138 0x11e 0 0 0
0139 0x11f 0 0 0>;
0140 };
0141
0142 timer@42100 {
0143 compatible = "fsl,mpic-global-timer";
0144 reg = <0x42100 0x100 0x42300 4>;
0145 interrupts = <4 0 3 0
0146 5 0 3 0
0147 6 0 3 0
0148 7 0 3 0>;
0149 };
