0001 /*
0002 * P5040 Silicon/SoC Device Tree Source (pre include)
0003 *
0004 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * This software is provided by Freescale Semiconductor "as is" and any
0024 * express or implied warranties, including, but not limited to, the implied
0025 * warranties of merchantability and fitness for a particular purpose are
0026 * disclaimed. In no event shall Freescale Semiconductor be liable for any
0027 * direct, indirect, incidental, special, exemplary, or consequential damages
0028 * (including, but not limited to, procurement of substitute goods or services;
0029 * loss of use, data, or profits; or business interruption) however caused and
0030 * on any theory of liability, whether in contract, strict liability, or tort
0031 * (including negligence or otherwise) arising in any way out of the use of this
0032 * software, even if advised of the possibility of such damage.
0033 */
0034
0035 /dts-v1/;
0036
0037 /include/ "e5500_power_isa.dtsi"
0038
0039 / {
0040 compatible = "fsl,P5040";
0041 #address-cells = <2>;
0042 #size-cells = <2>;
0043 interrupt-parent = <&mpic>;
0044
0045 aliases {
0046 ccsr = &soc;
0047 dcsr = &dcsr;
0048
0049 serial0 = &serial0;
0050 serial1 = &serial1;
0051 serial2 = &serial2;
0052 serial3 = &serial3;
0053 pci0 = &pci0;
0054 pci1 = &pci1;
0055 pci2 = &pci2;
0056 usb0 = &usb0;
0057 usb1 = &usb1;
0058 dma0 = &dma0;
0059 dma1 = &dma1;
0060 sdhc = &sdhc;
0061 msi0 = &msi0;
0062 msi1 = &msi1;
0063 msi2 = &msi2;
0064
0065 crypto = &crypto;
0066 sec_jr0 = &sec_jr0;
0067 sec_jr1 = &sec_jr1;
0068 sec_jr2 = &sec_jr2;
0069 sec_jr3 = &sec_jr3;
0070 rtic_a = &rtic_a;
0071 rtic_b = &rtic_b;
0072 rtic_c = &rtic_c;
0073 rtic_d = &rtic_d;
0074 sec_mon = &sec_mon;
0075
0076 raideng = &raideng;
0077 raideng_jr0 = &raideng_jr0;
0078 raideng_jr1 = &raideng_jr1;
0079 raideng_jr2 = &raideng_jr2;
0080 raideng_jr3 = &raideng_jr3;
0081
0082 fman0 = &fman0;
0083 fman1 = &fman1;
0084 ethernet0 = &enet0;
0085 ethernet1 = &enet1;
0086 ethernet2 = &enet2;
0087 ethernet3 = &enet3;
0088 ethernet4 = &enet4;
0089 ethernet5 = &enet5;
0090 ethernet6 = &enet6;
0091 ethernet7 = &enet7;
0092 ethernet8 = &enet8;
0093 ethernet9 = &enet9;
0094 ethernet10 = &enet10;
0095 ethernet11 = &enet11;
0096 };
0097
0098 cpus {
0099 #address-cells = <1>;
0100 #size-cells = <0>;
0101
0102 cpu0: PowerPC,e5500@0 {
0103 device_type = "cpu";
0104 reg = <0>;
0105 clocks = <&clockgen 1 0>;
0106 next-level-cache = <&L2_0>;
0107 fsl,portid-mapping = <0x80000000>;
0108 L2_0: l2-cache {
0109 next-level-cache = <&cpc>;
0110 };
0111 };
0112 cpu1: PowerPC,e5500@1 {
0113 device_type = "cpu";
0114 reg = <1>;
0115 clocks = <&clockgen 1 1>;
0116 next-level-cache = <&L2_1>;
0117 fsl,portid-mapping = <0x40000000>;
0118 L2_1: l2-cache {
0119 next-level-cache = <&cpc>;
0120 };
0121 };
0122 cpu2: PowerPC,e5500@2 {
0123 device_type = "cpu";
0124 reg = <2>;
0125 clocks = <&clockgen 1 2>;
0126 next-level-cache = <&L2_2>;
0127 fsl,portid-mapping = <0x20000000>;
0128 L2_2: l2-cache {
0129 next-level-cache = <&cpc>;
0130 };
0131 };
0132 cpu3: PowerPC,e5500@3 {
0133 device_type = "cpu";
0134 reg = <3>;
0135 clocks = <&clockgen 1 3>;
0136 next-level-cache = <&L2_3>;
0137 fsl,portid-mapping = <0x10000000>;
0138 L2_3: l2-cache {
0139 next-level-cache = <&cpc>;
0140 };
0141 };
0142 };
0143 };
