0001 /*
0002 * P5040DS Device Tree Source
0003 *
0004 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * This software is provided by Freescale Semiconductor "as is" and any
0024 * express or implied warranties, including, but not limited to, the implied
0025 * warranties of merchantability and fitness for a particular purpose are
0026 * disclaimed. In no event shall Freescale Semiconductor be liable for any
0027 * direct, indirect, incidental, special, exemplary, or consequential damages
0028 * (including, but not limited to, procurement of substitute goods or services;
0029 * loss of use, data, or profits; or business interruption) however caused and
0030 * on any theory of liability, whether in contract, strict liability, or tort
0031 * (including negligence or otherwise) arising in any way out of the use of this
0032 * software, even if advised of the possibility of such damage.
0033 */
0034
0035 /include/ "p5040si-pre.dtsi"
0036
0037 / {
0038 model = "fsl,P5040DS";
0039 compatible = "fsl,P5040DS";
0040 #address-cells = <2>;
0041 #size-cells = <2>;
0042 interrupt-parent = <&mpic>;
0043
0044 aliases{
0045 phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
0046 phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
0047 phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
0048 phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
0049 phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
0050 phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
0051 phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
0052 phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
0053 phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
0054 phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
0055 phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
0056 phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
0057 phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
0058 phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
0059 phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
0060 phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
0061 hydra_rg = &hydra_rg;
0062 hydra_sg_slot2 = &hydra_sg_slot2;
0063 hydra_sg_slot3 = &hydra_sg_slot3;
0064 hydra_sg_slot5 = &hydra_sg_slot5;
0065 hydra_sg_slot6 = &hydra_sg_slot6;
0066 hydra_xg_slot1 = &hydra_xg_slot1;
0067 hydra_xg_slot2 = &hydra_xg_slot2;
0068 };
0069
0070 memory {
0071 device_type = "memory";
0072 };
0073
0074 reserved-memory {
0075 #address-cells = <2>;
0076 #size-cells = <2>;
0077 ranges;
0078
0079 bman_fbpr: bman-fbpr {
0080 size = <0 0x1000000>;
0081 alignment = <0 0x1000000>;
0082 };
0083 qman_fqd: qman-fqd {
0084 size = <0 0x400000>;
0085 alignment = <0 0x400000>;
0086 };
0087 qman_pfdr: qman-pfdr {
0088 size = <0 0x2000000>;
0089 alignment = <0 0x2000000>;
0090 };
0091 };
0092
0093 dcsr: dcsr@f00000000 {
0094 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
0095 };
0096
0097 bportals: bman-portals@ff4000000 {
0098 ranges = <0x0 0xf 0xf4000000 0x200000>;
0099 };
0100
0101 qportals: qman-portals@ff4200000 {
0102 ranges = <0x0 0xf 0xf4200000 0x200000>;
0103 };
0104
0105 soc: soc@ffe000000 {
0106 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
0107 reg = <0xf 0xfe000000 0 0x00001000>;
0108 spi@110000 {
0109 flash@0 {
0110 #address-cells = <1>;
0111 #size-cells = <1>;
0112 compatible = "spansion,s25sl12801", "jedec,spi-nor";
0113 reg = <0>;
0114 spi-max-frequency = <40000000>; /* input clock */
0115 partition@u-boot {
0116 label = "u-boot";
0117 reg = <0x00000000 0x00100000>;
0118 };
0119 partition@kernel {
0120 label = "kernel";
0121 reg = <0x00100000 0x00500000>;
0122 };
0123 partition@dtb {
0124 label = "dtb";
0125 reg = <0x00600000 0x00100000>;
0126 };
0127 partition@fs {
0128 label = "file system";
0129 reg = <0x00700000 0x00900000>;
0130 };
0131 };
0132 };
0133
0134 i2c@118100 {
0135 eeprom@51 {
0136 compatible = "atmel,24c256";
0137 reg = <0x51>;
0138 };
0139 eeprom@52 {
0140 compatible = "atmel,24c256";
0141 reg = <0x52>;
0142 };
0143 };
0144
0145 i2c@119100 {
0146 rtc@68 {
0147 compatible = "dallas,ds3232";
0148 reg = <0x68>;
0149 interrupts = <0x1 0x1 0 0>;
0150 };
0151 ina220@40 {
0152 compatible = "ti,ina220";
0153 reg = <0x40>;
0154 shunt-resistor = <1000>;
0155 };
0156 ina220@41 {
0157 compatible = "ti,ina220";
0158 reg = <0x41>;
0159 shunt-resistor = <1000>;
0160 };
0161 ina220@44 {
0162 compatible = "ti,ina220";
0163 reg = <0x44>;
0164 shunt-resistor = <1000>;
0165 };
0166 ina220@45 {
0167 compatible = "ti,ina220";
0168 reg = <0x45>;
0169 shunt-resistor = <1000>;
0170 };
0171 adt7461@4c {
0172 compatible = "adi,adt7461";
0173 reg = <0x4c>;
0174 };
0175 };
0176
0177 fman@400000 {
0178 ethernet@e0000 {
0179 phy-connection-type = "sgmii";
0180 };
0181
0182 ethernet@e2000 {
0183 phy-connection-type = "sgmii";
0184 };
0185
0186 ethernet@e4000 {
0187 phy-connection-type = "sgmii";
0188 };
0189
0190 ethernet@e6000 {
0191 phy-connection-type = "sgmii";
0192 };
0193
0194 ethernet@e8000 {
0195 phy-handle = <&phy_rgmii_0>;
0196 phy-connection-type = "rgmii";
0197 };
0198
0199 ethernet@f0000 {
0200 phy-handle = <&phy_xgmii_slot_2>;
0201 phy-connection-type = "xgmii";
0202 };
0203 };
0204
0205 fman@500000 {
0206 ethernet@e0000 {
0207 phy-connection-type = "sgmii";
0208 };
0209
0210 ethernet@e2000 {
0211 phy-connection-type = "sgmii";
0212 };
0213
0214 ethernet@e4000 {
0215 phy-connection-type = "sgmii";
0216 };
0217
0218 ethernet@e6000 {
0219 phy-connection-type = "sgmii";
0220 };
0221
0222 ethernet@e8000 {
0223 phy-handle = <&phy_rgmii_1>;
0224 phy-connection-type = "rgmii";
0225 };
0226
0227 ethernet@f0000 {
0228 phy-handle = <&phy_xgmii_slot_1>;
0229 phy-connection-type = "xgmii";
0230 };
0231 };
0232 };
0233
0234 lbc: localbus@ffe124000 {
0235 reg = <0xf 0xfe124000 0 0x1000>;
0236 ranges = <0 0 0xf 0xe8000000 0x08000000
0237 2 0 0xf 0xffa00000 0x00040000
0238 3 0 0xf 0xffdf0000 0x00008000>;
0239
0240 flash@0,0 {
0241 compatible = "cfi-flash";
0242 reg = <0 0 0x08000000>;
0243 bank-width = <2>;
0244 device-width = <2>;
0245 };
0246
0247 nand@2,0 {
0248 #address-cells = <1>;
0249 #size-cells = <1>;
0250 compatible = "fsl,elbc-fcm-nand";
0251 reg = <0x2 0x0 0x40000>;
0252
0253 partition@0 {
0254 label = "NAND U-Boot Image";
0255 reg = <0x0 0x02000000>;
0256 };
0257
0258 partition@2000000 {
0259 label = "NAND Root File System";
0260 reg = <0x02000000 0x10000000>;
0261 };
0262
0263 partition@12000000 {
0264 label = "NAND Compressed RFS Image";
0265 reg = <0x12000000 0x08000000>;
0266 };
0267
0268 partition@1a000000 {
0269 label = "NAND Linux Kernel Image";
0270 reg = <0x1a000000 0x04000000>;
0271 };
0272
0273 partition@1e000000 {
0274 label = "NAND DTB Image";
0275 reg = <0x1e000000 0x01000000>;
0276 };
0277
0278 partition@1f000000 {
0279 label = "NAND Writable User area";
0280 reg = <0x1f000000 0x01000000>;
0281 };
0282 };
0283
0284 board-control@3,0 {
0285 #address-cells = <1>;
0286 #size-cells = <1>;
0287 compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
0288 reg = <3 0 0x40>;
0289 ranges = <0 3 0 0x40>;
0290
0291 mdio-mux-emi1 {
0292 #address-cells = <1>;
0293 #size-cells = <0>;
0294 compatible = "mdio-mux-mmioreg", "mdio-mux";
0295 mdio-parent-bus = <&mdio0>;
0296 reg = <9 1>;
0297 mux-mask = <0x78>;
0298
0299 hydra_rg:rgmii-mdio@8 {
0300 #address-cells = <1>;
0301 #size-cells = <0>;
0302 reg = <8>;
0303 status = "disabled";
0304
0305 phy_rgmii_0: ethernet-phy@0 {
0306 reg = <0x0>;
0307 };
0308
0309 phy_rgmii_1: ethernet-phy@1 {
0310 reg = <0x1>;
0311 };
0312 };
0313
0314 hydra_sg_slot2: sgmii-mdio@28 {
0315 #address-cells = <1>;
0316 #size-cells = <0>;
0317 reg = <0x28>;
0318 status = "disabled";
0319
0320 phy_sgmii_slot2_1c: ethernet-phy@1c {
0321 reg = <0x1c>;
0322 };
0323
0324 phy_sgmii_slot2_1d: ethernet-phy@1d {
0325 reg = <0x1d>;
0326 };
0327
0328 phy_sgmii_slot2_1e: ethernet-phy@1e {
0329 reg = <0x1e>;
0330 };
0331
0332 phy_sgmii_slot2_1f: ethernet-phy@1f {
0333 reg = <0x1f>;
0334 };
0335 };
0336
0337 hydra_sg_slot3: sgmii-mdio@68 {
0338 #address-cells = <1>;
0339 #size-cells = <0>;
0340 reg = <0x68>;
0341 status = "disabled";
0342
0343 phy_sgmii_slot3_1c: ethernet-phy@1c {
0344 reg = <0x1c>;
0345 };
0346
0347 phy_sgmii_slot3_1d: ethernet-phy@1d {
0348 reg = <0x1d>;
0349 };
0350
0351 phy_sgmii_slot3_1e: ethernet-phy@1e {
0352 reg = <0x1e>;
0353 };
0354
0355 phy_sgmii_slot3_1f: ethernet-phy@1f {
0356 reg = <0x1f>;
0357 };
0358 };
0359
0360 hydra_sg_slot5: sgmii-mdio@38 {
0361 #address-cells = <1>;
0362 #size-cells = <0>;
0363 reg = <0x38>;
0364 status = "disabled";
0365
0366 phy_sgmii_slot5_1c: ethernet-phy@1c {
0367 reg = <0x1c>;
0368 };
0369
0370 phy_sgmii_slot5_1d: ethernet-phy@1d {
0371 reg = <0x1d>;
0372 };
0373
0374 phy_sgmii_slot5_1e: ethernet-phy@1e {
0375 reg = <0x1e>;
0376 };
0377
0378 phy_sgmii_slot5_1f: ethernet-phy@1f {
0379 reg = <0x1f>;
0380 };
0381 };
0382 hydra_sg_slot6: sgmii-mdio@48 {
0383 #address-cells = <1>;
0384 #size-cells = <0>;
0385 reg = <0x48>;
0386 status = "disabled";
0387
0388 phy_sgmii_slot6_1c: ethernet-phy@1c {
0389 reg = <0x1c>;
0390 };
0391
0392 phy_sgmii_slot6_1d: ethernet-phy@1d {
0393 reg = <0x1d>;
0394 };
0395
0396 phy_sgmii_slot6_1e: ethernet-phy@1e {
0397 reg = <0x1e>;
0398 };
0399
0400 phy_sgmii_slot6_1f: ethernet-phy@1f {
0401 reg = <0x1f>;
0402 };
0403 };
0404 };
0405
0406 mdio-mux-emi2 {
0407 #address-cells = <1>;
0408 #size-cells = <0>;
0409 compatible = "mdio-mux-mmioreg", "mdio-mux";
0410 mdio-parent-bus = <&xmdio0>;
0411 reg = <9 1>;
0412 mux-mask = <0x06>;
0413
0414 hydra_xg_slot1: hydra-xg-slot1@0 {
0415 #address-cells = <1>;
0416 #size-cells = <0>;
0417 reg = <0>;
0418 status = "disabled";
0419
0420 phy_xgmii_slot_1: ethernet-phy@0 {
0421 compatible = "ethernet-phy-ieee802.3-c45";
0422 reg = <4>;
0423 };
0424 };
0425
0426 hydra_xg_slot2: hydra-xg-slot2@2 {
0427 #address-cells = <1>;
0428 #size-cells = <0>;
0429 reg = <2>;
0430
0431 phy_xgmii_slot_2: ethernet-phy@4 {
0432 compatible = "ethernet-phy-ieee802.3-c45";
0433 reg = <0>;
0434 };
0435 };
0436 };
0437 };
0438 };
0439
0440 pci0: pcie@ffe200000 {
0441 reg = <0xf 0xfe200000 0 0x1000>;
0442 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0443 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
0444 pcie@0 {
0445 ranges = <0x02000000 0 0xe0000000
0446 0x02000000 0 0xe0000000
0447 0 0x20000000
0448
0449 0x01000000 0 0x00000000
0450 0x01000000 0 0x00000000
0451 0 0x00010000>;
0452 };
0453 };
0454
0455 pci1: pcie@ffe201000 {
0456 reg = <0xf 0xfe201000 0 0x1000>;
0457 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0458 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
0459 pcie@0 {
0460 ranges = <0x02000000 0 0xe0000000
0461 0x02000000 0 0xe0000000
0462 0 0x20000000
0463
0464 0x01000000 0 0x00000000
0465 0x01000000 0 0x00000000
0466 0 0x00010000>;
0467 };
0468 };
0469
0470 pci2: pcie@ffe202000 {
0471 reg = <0xf 0xfe202000 0 0x1000>;
0472 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0473 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
0474 pcie@0 {
0475 ranges = <0x02000000 0 0xe0000000
0476 0x02000000 0 0xe0000000
0477 0 0x20000000
0478
0479 0x01000000 0 0x00000000
0480 0x01000000 0 0x00000000
0481 0 0x00010000>;
0482 };
0483 };
0484 };
0485
0486 /include/ "p5040si-post.dtsi"
