0001 /*
0002 * P5020/P5010 Silicon/SoC Device Tree Source (pre include)
0003 *
0004 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 /dts-v1/;
0036
0037 /include/ "e5500_power_isa.dtsi"
0038
0039 / {
0040 compatible = "fsl,P5020";
0041 #address-cells = <2>;
0042 #size-cells = <2>;
0043 interrupt-parent = <&mpic>;
0044
0045 aliases {
0046 ccsr = &soc;
0047 dcsr = &dcsr;
0048
0049 serial0 = &serial0;
0050 serial1 = &serial1;
0051 serial2 = &serial2;
0052 serial3 = &serial3;
0053 pci0 = &pci0;
0054 pci1 = &pci1;
0055 pci2 = &pci2;
0056 pci3 = &pci3;
0057 usb0 = &usb0;
0058 usb1 = &usb1;
0059 dma0 = &dma0;
0060 dma1 = &dma1;
0061 sdhc = &sdhc;
0062 msi0 = &msi0;
0063 msi1 = &msi1;
0064 msi2 = &msi2;
0065
0066 crypto = &crypto;
0067 sec_jr0 = &sec_jr0;
0068 sec_jr1 = &sec_jr1;
0069 sec_jr2 = &sec_jr2;
0070 sec_jr3 = &sec_jr3;
0071 rtic_a = &rtic_a;
0072 rtic_b = &rtic_b;
0073 rtic_c = &rtic_c;
0074 rtic_d = &rtic_d;
0075 sec_mon = &sec_mon;
0076
0077 raideng = &raideng;
0078 raideng_jr0 = &raideng_jr0;
0079 raideng_jr1 = &raideng_jr1;
0080 raideng_jr2 = &raideng_jr2;
0081 raideng_jr3 = &raideng_jr3;
0082
0083 fman0 = &fman0;
0084 ethernet0 = &enet0;
0085 ethernet1 = &enet1;
0086 ethernet2 = &enet2;
0087 ethernet3 = &enet3;
0088 ethernet4 = &enet4;
0089 ethernet5 = &enet5;
0090 };
0091
0092 cpus {
0093 #address-cells = <1>;
0094 #size-cells = <0>;
0095
0096 cpu0: PowerPC,e5500@0 {
0097 device_type = "cpu";
0098 reg = <0>;
0099 clocks = <&clockgen 1 0>;
0100 next-level-cache = <&L2_0>;
0101 fsl,portid-mapping = <0x80000000>;
0102 L2_0: l2-cache {
0103 next-level-cache = <&cpc>;
0104 };
0105 };
0106 cpu1: PowerPC,e5500@1 {
0107 device_type = "cpu";
0108 reg = <1>;
0109 clocks = <&clockgen 1 1>;
0110 next-level-cache = <&L2_1>;
0111 fsl,portid-mapping = <0x40000000>;
0112 L2_1: l2-cache {
0113 next-level-cache = <&cpc>;
0114 };
0115 };
0116 };
0117 };
