0001 /*
0002 * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
0003 *
0004 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 /dts-v1/;
0036
0037 /include/ "e500mc_power_isa.dtsi"
0038
0039 / {
0040 compatible = "fsl,P4080";
0041 #address-cells = <2>;
0042 #size-cells = <2>;
0043 interrupt-parent = <&mpic>;
0044
0045 aliases {
0046 ccsr = &soc;
0047 dcsr = &dcsr;
0048
0049 serial0 = &serial0;
0050 serial1 = &serial1;
0051 serial2 = &serial2;
0052 serial3 = &serial3;
0053 pci0 = &pci0;
0054 pci1 = &pci1;
0055 pci2 = &pci2;
0056 usb0 = &usb0;
0057 usb1 = &usb1;
0058 dma0 = &dma0;
0059 dma1 = &dma1;
0060 sdhc = &sdhc;
0061 msi0 = &msi0;
0062 msi1 = &msi1;
0063 msi2 = &msi2;
0064
0065 crypto = &crypto;
0066 sec_jr0 = &sec_jr0;
0067 sec_jr1 = &sec_jr1;
0068 sec_jr2 = &sec_jr2;
0069 sec_jr3 = &sec_jr3;
0070 rtic_a = &rtic_a;
0071 rtic_b = &rtic_b;
0072 rtic_c = &rtic_c;
0073 rtic_d = &rtic_d;
0074 sec_mon = &sec_mon;
0075
0076 fman0 = &fman0;
0077 fman1 = &fman1;
0078 ethernet0 = &enet0;
0079 ethernet1 = &enet1;
0080 ethernet2 = &enet2;
0081 ethernet3 = &enet3;
0082 ethernet4 = &enet4;
0083 ethernet5 = &enet5;
0084 ethernet6 = &enet6;
0085 ethernet7 = &enet7;
0086 ethernet8 = &enet8;
0087 ethernet9 = &enet9;
0088 };
0089
0090 cpus {
0091 #address-cells = <1>;
0092 #size-cells = <0>;
0093
0094 cpu0: PowerPC,e500mc@0 {
0095 device_type = "cpu";
0096 reg = <0>;
0097 clocks = <&clockgen 1 0>;
0098 next-level-cache = <&L2_0>;
0099 fsl,portid-mapping = <0x80000000>;
0100 L2_0: l2-cache {
0101 next-level-cache = <&cpc>;
0102 };
0103 };
0104 cpu1: PowerPC,e500mc@1 {
0105 device_type = "cpu";
0106 reg = <1>;
0107 clocks = <&clockgen 1 1>;
0108 next-level-cache = <&L2_1>;
0109 fsl,portid-mapping = <0x40000000>;
0110 L2_1: l2-cache {
0111 next-level-cache = <&cpc>;
0112 };
0113 };
0114 cpu2: PowerPC,e500mc@2 {
0115 device_type = "cpu";
0116 reg = <2>;
0117 clocks = <&clockgen 1 2>;
0118 next-level-cache = <&L2_2>;
0119 fsl,portid-mapping = <0x20000000>;
0120 L2_2: l2-cache {
0121 next-level-cache = <&cpc>;
0122 };
0123 };
0124 cpu3: PowerPC,e500mc@3 {
0125 device_type = "cpu";
0126 reg = <3>;
0127 clocks = <&clockgen 1 3>;
0128 next-level-cache = <&L2_3>;
0129 fsl,portid-mapping = <0x10000000>;
0130 L2_3: l2-cache {
0131 next-level-cache = <&cpc>;
0132 };
0133 };
0134 cpu4: PowerPC,e500mc@4 {
0135 device_type = "cpu";
0136 reg = <4>;
0137 clocks = <&clockgen 1 4>;
0138 next-level-cache = <&L2_4>;
0139 fsl,portid-mapping = <0x08000000>;
0140 L2_4: l2-cache {
0141 next-level-cache = <&cpc>;
0142 };
0143 };
0144 cpu5: PowerPC,e500mc@5 {
0145 device_type = "cpu";
0146 reg = <5>;
0147 clocks = <&clockgen 1 5>;
0148 next-level-cache = <&L2_5>;
0149 fsl,portid-mapping = <0x04000000>;
0150 L2_5: l2-cache {
0151 next-level-cache = <&cpc>;
0152 };
0153 };
0154 cpu6: PowerPC,e500mc@6 {
0155 device_type = "cpu";
0156 reg = <6>;
0157 clocks = <&clockgen 1 6>;
0158 next-level-cache = <&L2_6>;
0159 fsl,portid-mapping = <0x02000000>;
0160 L2_6: l2-cache {
0161 next-level-cache = <&cpc>;
0162 };
0163 };
0164 cpu7: PowerPC,e500mc@7 {
0165 device_type = "cpu";
0166 reg = <7>;
0167 clocks = <&clockgen 1 7>;
0168 next-level-cache = <&L2_7>;
0169 fsl,portid-mapping = <0x01000000>;
0170 L2_7: l2-cache {
0171 next-level-cache = <&cpc>;
0172 };
0173 };
0174 };
0175 };
