0001 /*
0002 * P3041DS Device Tree Source
0003 *
0004 * Copyright 2010 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 /include/ "p3041si-pre.dtsi"
0036
0037 / {
0038 model = "fsl,P3041DS";
0039 compatible = "fsl,P3041DS";
0040 #address-cells = <2>;
0041 #size-cells = <2>;
0042 interrupt-parent = <&mpic>;
0043
0044 aliases{
0045 phy_rgmii_0 = &phy_rgmii_0;
0046 phy_rgmii_1 = &phy_rgmii_1;
0047 phy_sgmii_1c = &phy_sgmii_1c;
0048 phy_sgmii_1d = &phy_sgmii_1d;
0049 phy_sgmii_1e = &phy_sgmii_1e;
0050 phy_sgmii_1f = &phy_sgmii_1f;
0051 phy_xgmii_1 = &phy_xgmii_1;
0052 phy_xgmii_2 = &phy_xgmii_2;
0053 emi1_rgmii = &hydra_mdio_rgmii;
0054 emi1_sgmii = &hydra_mdio_sgmii;
0055 emi2_xgmii = &hydra_mdio_xgmii;
0056 };
0057
0058 memory {
0059 device_type = "memory";
0060 };
0061
0062 reserved-memory {
0063 #address-cells = <2>;
0064 #size-cells = <2>;
0065 ranges;
0066
0067 bman_fbpr: bman-fbpr {
0068 size = <0 0x1000000>;
0069 alignment = <0 0x1000000>;
0070 };
0071 qman_fqd: qman-fqd {
0072 size = <0 0x400000>;
0073 alignment = <0 0x400000>;
0074 };
0075 qman_pfdr: qman-pfdr {
0076 size = <0 0x2000000>;
0077 alignment = <0 0x2000000>;
0078 };
0079 };
0080
0081 dcsr: dcsr@f00000000 {
0082 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
0083 };
0084
0085 bportals: bman-portals@ff4000000 {
0086 ranges = <0x0 0xf 0xf4000000 0x200000>;
0087 };
0088
0089 qportals: qman-portals@ff4200000 {
0090 ranges = <0x0 0xf 0xf4200000 0x200000>;
0091 };
0092
0093 soc: soc@ffe000000 {
0094 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
0095 reg = <0xf 0xfe000000 0 0x00001000>;
0096 spi@110000 {
0097 flash@0 {
0098 #address-cells = <1>;
0099 #size-cells = <1>;
0100 compatible = "spansion,s25sl12801", "jedec,spi-nor";
0101 reg = <0>;
0102 spi-max-frequency = <35000000>; /* input clock */
0103 partition@u-boot {
0104 label = "u-boot";
0105 reg = <0x00000000 0x00100000>;
0106 read-only;
0107 };
0108 partition@kernel {
0109 label = "kernel";
0110 reg = <0x00100000 0x00500000>;
0111 read-only;
0112 };
0113 partition@dtb {
0114 label = "dtb";
0115 reg = <0x00600000 0x00100000>;
0116 read-only;
0117 };
0118 partition@fs {
0119 label = "file system";
0120 reg = <0x00700000 0x00900000>;
0121 };
0122 };
0123 };
0124
0125 i2c@118100 {
0126 eeprom@51 {
0127 compatible = "atmel,24c256";
0128 reg = <0x51>;
0129 };
0130 eeprom@52 {
0131 compatible = "atmel,24c256";
0132 reg = <0x52>;
0133 };
0134 };
0135
0136 i2c@119100 {
0137 rtc@68 {
0138 compatible = "dallas,ds3232";
0139 reg = <0x68>;
0140 interrupts = <0x1 0x1 0 0>;
0141 };
0142 ina220@40 {
0143 compatible = "ti,ina220";
0144 reg = <0x40>;
0145 shunt-resistor = <1000>;
0146 };
0147 ina220@41 {
0148 compatible = "ti,ina220";
0149 reg = <0x41>;
0150 shunt-resistor = <1000>;
0151 };
0152 ina220@44 {
0153 compatible = "ti,ina220";
0154 reg = <0x44>;
0155 shunt-resistor = <1000>;
0156 };
0157 ina220@45 {
0158 compatible = "ti,ina220";
0159 reg = <0x45>;
0160 shunt-resistor = <1000>;
0161 };
0162 adt7461@4c {
0163 compatible = "adi,adt7461";
0164 reg = <0x4c>;
0165 };
0166 };
0167
0168 fman@400000{
0169 ethernet@e0000 {
0170 phy-handle = <&phy_sgmii_1c>;
0171 phy-connection-type = "sgmii";
0172 };
0173
0174 ethernet@e2000 {
0175 phy-handle = <&phy_sgmii_1d>;
0176 phy-connection-type = "sgmii";
0177 };
0178
0179 ethernet@e4000 {
0180 phy-handle = <&phy_sgmii_1e>;
0181 phy-connection-type = "sgmii";
0182 };
0183
0184 ethernet@e6000 {
0185 phy-handle = <&phy_sgmii_1f>;
0186 phy-connection-type = "sgmii";
0187 };
0188
0189 ethernet@e8000 {
0190 phy-handle = <&phy_rgmii_1>;
0191 phy-connection-type = "rgmii";
0192 };
0193
0194 ethernet@f0000 {
0195 phy-handle = <&phy_xgmii_1>;
0196 phy-connection-type = "xgmii";
0197 };
0198
0199 hydra_mdio_xgmii: mdio@f1000 {
0200 status = "disabled";
0201
0202 phy_xgmii_1: ethernet-phy@4 {
0203 compatible = "ethernet-phy-ieee802.3-c45";
0204 reg = <0x4>;
0205 };
0206
0207 phy_xgmii_2: ethernet-phy@0 {
0208 compatible = "ethernet-phy-ieee802.3-c45";
0209 reg = <0x0>;
0210 };
0211 };
0212 };
0213 };
0214
0215 rio: rapidio@ffe0c0000 {
0216 reg = <0xf 0xfe0c0000 0 0x11000>;
0217
0218 port1 {
0219 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
0220 };
0221 port2 {
0222 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
0223 };
0224 };
0225
0226 lbc: localbus@ffe124000 {
0227 reg = <0xf 0xfe124000 0 0x1000>;
0228 ranges = <0 0 0xf 0xe8000000 0x08000000
0229 2 0 0xf 0xffa00000 0x00040000
0230 3 0 0xf 0xffdf0000 0x00008000>;
0231
0232 flash@0,0 {
0233 compatible = "cfi-flash";
0234 reg = <0 0 0x08000000>;
0235 bank-width = <2>;
0236 device-width = <2>;
0237 };
0238
0239 nand@2,0 {
0240 #address-cells = <1>;
0241 #size-cells = <1>;
0242 compatible = "fsl,elbc-fcm-nand";
0243 reg = <0x2 0x0 0x40000>;
0244
0245 partition@0 {
0246 label = "NAND U-Boot Image";
0247 reg = <0x0 0x02000000>;
0248 read-only;
0249 };
0250
0251 partition@2000000 {
0252 label = "NAND Root File System";
0253 reg = <0x02000000 0x10000000>;
0254 };
0255
0256 partition@12000000 {
0257 label = "NAND Compressed RFS Image";
0258 reg = <0x12000000 0x08000000>;
0259 };
0260
0261 partition@1a000000 {
0262 label = "NAND Linux Kernel Image";
0263 reg = <0x1a000000 0x04000000>;
0264 };
0265
0266 partition@1e000000 {
0267 label = "NAND DTB Image";
0268 reg = <0x1e000000 0x01000000>;
0269 };
0270
0271 partition@1f000000 {
0272 label = "NAND Writable User area";
0273 reg = <0x1f000000 0x21000000>;
0274 };
0275 };
0276
0277 board-control@3,0 {
0278 #address-cells = <1>;
0279 #size-cells = <1>;
0280 compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
0281 reg = <3 0 0x30>;
0282 ranges = <0 3 0 0x30>;
0283
0284 mdio-mux-emi1 {
0285 #address-cells = <1>;
0286 #size-cells = <0>;
0287 compatible = "mdio-mux-mmioreg", "mdio-mux";
0288 mdio-parent-bus = <&mdio0>;
0289 reg = <9 1>;
0290 mux-mask = <0x78>;
0291
0292 hydra_mdio_rgmii: rgmii-mdio@8 {
0293 #address-cells = <1>;
0294 #size-cells = <0>;
0295 reg = <8>;
0296 status = "disabled";
0297
0298 phy_rgmii_0: ethernet-phy@0 {
0299 reg = <0x0>;
0300 };
0301
0302 phy_rgmii_1: ethernet-phy@1 {
0303 reg = <0x1>;
0304 };
0305 };
0306
0307 hydra_mdio_sgmii: sgmii-mdio@28 {
0308 #address-cells = <1>;
0309 #size-cells = <0>;
0310 reg = <0x28>;
0311 status = "disabled";
0312
0313 phy_sgmii_1c: ethernet-phy@1c {
0314 reg = <0x1c>;
0315 };
0316
0317 phy_sgmii_1d: ethernet-phy@1d {
0318 reg = <0x1d>;
0319 };
0320
0321 phy_sgmii_1e: ethernet-phy@1e {
0322 reg = <0x1e>;
0323 };
0324
0325 phy_sgmii_1f: ethernet-phy@1f {
0326 reg = <0x1f>;
0327 };
0328 };
0329 };
0330 };
0331 };
0332
0333 pci0: pcie@ffe200000 {
0334 reg = <0xf 0xfe200000 0 0x1000>;
0335 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0336 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
0337 pcie@0 {
0338 ranges = <0x02000000 0 0xe0000000
0339 0x02000000 0 0xe0000000
0340 0 0x20000000
0341
0342 0x01000000 0 0x00000000
0343 0x01000000 0 0x00000000
0344 0 0x00010000>;
0345 };
0346 };
0347
0348 pci1: pcie@ffe201000 {
0349 reg = <0xf 0xfe201000 0 0x1000>;
0350 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0351 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
0352 pcie@0 {
0353 ranges = <0x02000000 0 0xe0000000
0354 0x02000000 0 0xe0000000
0355 0 0x20000000
0356
0357 0x01000000 0 0x00000000
0358 0x01000000 0 0x00000000
0359 0 0x00010000>;
0360 };
0361 };
0362
0363 pci2: pcie@ffe202000 {
0364 reg = <0xf 0xfe202000 0 0x1000>;
0365 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0366 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
0367 pcie@0 {
0368 ranges = <0x02000000 0 0xe0000000
0369 0x02000000 0 0xe0000000
0370 0 0x20000000
0371
0372 0x01000000 0 0x00000000
0373 0x01000000 0 0x00000000
0374 0 0x00010000>;
0375 };
0376 };
0377
0378 pci3: pcie@ffe203000 {
0379 reg = <0xf 0xfe203000 0 0x1000>;
0380 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
0381 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
0382 pcie@0 {
0383 ranges = <0x02000000 0 0xe0000000
0384 0x02000000 0 0xe0000000
0385 0 0x20000000
0386
0387 0x01000000 0 0x00000000
0388 0x01000000 0 0x00000000
0389 0 0x00010000>;
0390 };
0391 };
0392 };
0393
0394 /include/ "p3041si-post.dtsi"
