0001 /*
0002 * P2041RDB Device Tree Source
0003 *
0004 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 /include/ "p2041si-pre.dtsi"
0036
0037 / {
0038 model = "fsl,P2041RDB";
0039 compatible = "fsl,P2041RDB";
0040 #address-cells = <2>;
0041 #size-cells = <2>;
0042 interrupt-parent = <&mpic>;
0043
0044 aliases {
0045 phy_rgmii_0 = &phy_rgmii_0;
0046 phy_rgmii_1 = &phy_rgmii_1;
0047 phy_sgmii_2 = &phy_sgmii_2;
0048 phy_sgmii_3 = &phy_sgmii_3;
0049 phy_sgmii_4 = &phy_sgmii_4;
0050 phy_sgmii_1c = &phy_sgmii_1c;
0051 phy_sgmii_1d = &phy_sgmii_1d;
0052 phy_sgmii_1e = &phy_sgmii_1e;
0053 phy_sgmii_1f = &phy_sgmii_1f;
0054 phy_xgmii_2 = &phy_xgmii_2;
0055 };
0056
0057 memory {
0058 device_type = "memory";
0059 };
0060
0061 reserved-memory {
0062 #address-cells = <2>;
0063 #size-cells = <2>;
0064 ranges;
0065
0066 bman_fbpr: bman-fbpr {
0067 size = <0 0x1000000>;
0068 alignment = <0 0x1000000>;
0069 };
0070 qman_fqd: qman-fqd {
0071 size = <0 0x400000>;
0072 alignment = <0 0x400000>;
0073 };
0074 qman_pfdr: qman-pfdr {
0075 size = <0 0x2000000>;
0076 alignment = <0 0x2000000>;
0077 };
0078 };
0079
0080 dcsr: dcsr@f00000000 {
0081 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
0082 };
0083
0084 bportals: bman-portals@ff4000000 {
0085 ranges = <0x0 0xf 0xf4000000 0x200000>;
0086 };
0087
0088 qportals: qman-portals@ff4200000 {
0089 ranges = <0x0 0xf 0xf4200000 0x200000>;
0090 };
0091
0092 soc: soc@ffe000000 {
0093 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
0094 reg = <0xf 0xfe000000 0 0x00001000>;
0095 spi@110000 {
0096 flash@0 {
0097 #address-cells = <1>;
0098 #size-cells = <1>;
0099 compatible = "spansion,s25sl12801", "jedec,spi-nor";
0100 reg = <0>;
0101 spi-max-frequency = <40000000>; /* input clock */
0102 partition@u-boot {
0103 label = "u-boot";
0104 reg = <0x00000000 0x00100000>;
0105 read-only;
0106 };
0107 partition@kernel {
0108 label = "kernel";
0109 reg = <0x00100000 0x00500000>;
0110 read-only;
0111 };
0112 partition@dtb {
0113 label = "dtb";
0114 reg = <0x00600000 0x00100000>;
0115 read-only;
0116 };
0117 partition@fs {
0118 label = "file system";
0119 reg = <0x00700000 0x00900000>;
0120 };
0121 };
0122 };
0123
0124 i2c@118000 {
0125 lm75b@48 {
0126 compatible = "nxp,lm75a";
0127 reg = <0x48>;
0128 };
0129 eeprom@50 {
0130 compatible = "atmel,24c256";
0131 reg = <0x50>;
0132 };
0133 rtc@68 {
0134 compatible = "pericom,pt7c4338";
0135 reg = <0x68>;
0136 };
0137 adt7461@4c {
0138 compatible = "adi,adt7461";
0139 reg = <0x4c>;
0140 };
0141 };
0142
0143 i2c@118100 {
0144 eeprom@50 {
0145 compatible = "atmel,24c256";
0146 reg = <0x50>;
0147 };
0148 };
0149
0150 usb1: usb@211000 {
0151 dr_mode = "host";
0152 };
0153
0154 fman@400000 {
0155 ethernet@e0000 {
0156 phy-handle = <&phy_sgmii_2>;
0157 phy-connection-type = "sgmii";
0158 };
0159
0160 mdio@e1120 {
0161 phy_rgmii_0: ethernet-phy@0 {
0162 reg = <0x0>;
0163 };
0164
0165 phy_rgmii_1: ethernet-phy@1 {
0166 reg = <0x1>;
0167 };
0168
0169 phy_sgmii_2: ethernet-phy@2 {
0170 reg = <0x2>;
0171 };
0172
0173 phy_sgmii_3: ethernet-phy@3 {
0174 reg = <0x3>;
0175 };
0176
0177 phy_sgmii_4: ethernet-phy@4 {
0178 reg = <0x4>;
0179 };
0180
0181 phy_sgmii_1c: ethernet-phy@1c {
0182 reg = <0x1c>;
0183 };
0184
0185 phy_sgmii_1d: ethernet-phy@1d {
0186 reg = <0x1d>;
0187 };
0188
0189 phy_sgmii_1e: ethernet-phy@1e {
0190 reg = <0x1e>;
0191 };
0192
0193 phy_sgmii_1f: ethernet-phy@1f {
0194 reg = <0x1f>;
0195 };
0196 };
0197
0198 ethernet@e2000 {
0199 phy-handle = <&phy_sgmii_3>;
0200 phy-connection-type = "sgmii";
0201 };
0202
0203 ethernet@e4000 {
0204 phy-handle = <&phy_sgmii_4>;
0205 phy-connection-type = "sgmii";
0206 };
0207
0208 ethernet@e6000 {
0209 phy-handle = <&phy_rgmii_1>;
0210 phy-connection-type = "rgmii";
0211 };
0212
0213 ethernet@e8000 {
0214 phy-handle = <&phy_rgmii_0>;
0215 phy-connection-type = "rgmii";
0216 };
0217
0218 ethernet@f0000 {
0219 phy-handle = <&phy_xgmii_2>;
0220 phy-connection-type = "xgmii";
0221 };
0222
0223 mdio@f1000 {
0224 phy_xgmii_2: ethernet-phy@0 {
0225 compatible = "ethernet-phy-ieee802.3-c45";
0226 reg = <0x0>;
0227 };
0228 };
0229 };
0230 };
0231
0232 rio: rapidio@ffe0c0000 {
0233 reg = <0xf 0xfe0c0000 0 0x11000>;
0234
0235 port1 {
0236 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
0237 };
0238 port2 {
0239 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
0240 };
0241 };
0242
0243 lbc: localbus@ffe124000 {
0244 reg = <0xf 0xfe124000 0 0x1000>;
0245 ranges = <0 0 0xf 0xe8000000 0x08000000
0246 1 0 0xf 0xffa00000 0x00040000>;
0247
0248 flash@0,0 {
0249 compatible = "cfi-flash";
0250 reg = <0 0 0x08000000>;
0251 bank-width = <2>;
0252 device-width = <2>;
0253 };
0254
0255 nand@1,0 {
0256 #address-cells = <1>;
0257 #size-cells = <1>;
0258 compatible = "fsl,elbc-fcm-nand";
0259 reg = <0x1 0x0 0x40000>;
0260
0261 partition@0 {
0262 label = "NAND U-Boot Image";
0263 reg = <0x0 0x02000000>;
0264 read-only;
0265 };
0266
0267 partition@2000000 {
0268 label = "NAND Root File System";
0269 reg = <0x02000000 0x10000000>;
0270 };
0271
0272 partition@12000000 {
0273 label = "NAND Compressed RFS Image";
0274 reg = <0x12000000 0x08000000>;
0275 };
0276
0277 partition@1a000000 {
0278 label = "NAND Linux Kernel Image";
0279 reg = <0x1a000000 0x04000000>;
0280 };
0281
0282 partition@1e000000 {
0283 label = "NAND DTB Image";
0284 reg = <0x1e000000 0x01000000>;
0285 };
0286
0287 partition@1f000000 {
0288 label = "NAND Writable User area";
0289 reg = <0x1f000000 0x01000000>;
0290 };
0291 };
0292 };
0293
0294 pci0: pcie@ffe200000 {
0295 reg = <0xf 0xfe200000 0 0x1000>;
0296 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0297 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
0298 pcie@0 {
0299 ranges = <0x02000000 0 0xe0000000
0300 0x02000000 0 0xe0000000
0301 0 0x20000000
0302
0303 0x01000000 0 0x00000000
0304 0x01000000 0 0x00000000
0305 0 0x00010000>;
0306 };
0307 };
0308
0309 pci1: pcie@ffe201000 {
0310 reg = <0xf 0xfe201000 0 0x1000>;
0311 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0312 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
0313 pcie@0 {
0314 ranges = <0x02000000 0 0xe0000000
0315 0x02000000 0 0xe0000000
0316 0 0x20000000
0317
0318 0x01000000 0 0x00000000
0319 0x01000000 0 0x00000000
0320 0 0x00010000>;
0321 };
0322 };
0323
0324 pci2: pcie@ffe202000 {
0325 reg = <0xf 0xfe202000 0 0x1000>;
0326 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0327 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
0328 pcie@0 {
0329 ranges = <0x02000000 0 0xe0000000
0330 0x02000000 0 0xe0000000
0331 0 0x20000000
0332
0333 0x01000000 0 0x00000000
0334 0x01000000 0 0x00000000
0335 0 0x00010000>;
0336 };
0337 };
0338 };
0339
0340 /include/ "p2041si-post.dtsi"
