0001 /*
0002 * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
0003 *
0004 * Copyright 2013 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 /{
0036 aliases {
0037 ethernet3 = &enet3;
0038 ethernet4 = &enet4;
0039 };
0040 };
0041
0042 &lbc {
0043 nor@0,0 {
0044 #address-cells = <1>;
0045 #size-cells = <1>;
0046 compatible = "cfi-flash";
0047 reg = <0x0 0x0 0x4000000>;
0048 bank-width = <2>;
0049 device-width = <1>;
0050
0051 partition@0 {
0052 /* This location must not be altered */
0053 /* 256KB for Vitesse 7385 Switch firmware */
0054 reg = <0x0 0x00040000>;
0055 label = "NOR Vitesse-7385 Firmware";
0056 read-only;
0057 };
0058
0059 partition@40000 {
0060 /* 256KB for DTB Image */
0061 reg = <0x00040000 0x00040000>;
0062 label = "NOR DTB Image";
0063 };
0064
0065 partition@80000 {
0066 /* 5.5 MB for Linux Kernel Image */
0067 reg = <0x00080000 0x00580000>;
0068 label = "NOR Linux Kernel Image";
0069 };
0070
0071 partition@400000 {
0072 /* 56.75MB for Root file System */
0073 reg = <0x00600000 0x038c0000>;
0074 label = "NOR Root File System";
0075 };
0076
0077 partition@ec0000 {
0078 /* This location must not be altered */
0079 /* 256KB for QE ucode firmware*/
0080 reg = <0x03ec0000 0x00040000>;
0081 label = "NOR QE microcode firmware";
0082 read-only;
0083 };
0084
0085 partition@f00000 {
0086 /* This location must not be altered */
0087 /* 512KB for u-boot Bootloader Image */
0088 /* 512KB for u-boot Environment Variables */
0089 reg = <0x03f00000 0x00100000>;
0090 label = "NOR U-Boot Image";
0091 read-only;
0092 };
0093 };
0094
0095 /* CS2 for Display */
0096 display@2,0 {
0097 compatible = "solomon,ssd1289fb";
0098 reg = <0x2 0x0000 0x0004>;
0099 };
0100
0101 };
0102
0103 &soc {
0104 usb@22000 {
0105 phy_type = "ulpi";
0106 };
0107
0108 mdio@24000 {
0109 phy0: ethernet-phy@2 {
0110 interrupt-parent = <&mpic>;
0111 interrupts = <1 1 0 0>;
0112 reg = <0x2>;
0113 };
0114
0115 phy1: ethernet-phy@1 {
0116 interrupt-parent = <&mpic>;
0117 interrupts = <2 1 0 0>;
0118 reg = <0x1>;
0119 };
0120
0121 tbi0: tbi-phy@11 {
0122 reg = <0x11>;
0123 device_type = "tbi-phy";
0124 };
0125 };
0126
0127 mdio@25000 {
0128 tbi1: tbi-phy@11 {
0129 reg = <0x11>;
0130 device_type = "tbi-phy";
0131 };
0132 };
0133
0134 mdio@26000 {
0135 tbi2: tbi-phy@11 {
0136 reg = <0x11>;
0137 device_type = "tbi-phy";
0138 };
0139 };
0140
0141 ptp_clock@b0e00 {
0142 compatible = "fsl,etsec-ptp";
0143 reg = <0xb0e00 0xb0>;
0144 interrupts = <68 2 0 0 69 2 0 0>;
0145 fsl,tclk-period = <10>;
0146 fsl,tmr-prsc = <2>;
0147 fsl,tmr-add = <0xc0000021>;
0148 fsl,tmr-fiper1 = <999999990>;
0149 fsl,tmr-fiper2 = <99990>;
0150 fsl,max-adj = <133333332>;
0151 };
0152
0153 enet0: ethernet@b0000 {
0154 phy-handle = <&phy0>;
0155 phy-connection-type = "rgmii-id";
0156
0157 };
0158
0159 enet1: ethernet@b1000 {
0160 status = "disabled";
0161 };
0162
0163 enet2: ethernet@b2000 {
0164 phy-handle = <&phy1>;
0165 phy-connection-type = "rgmii-id";
0166 };
0167
0168 par_io@e0100 {
0169 #address-cells = <1>;
0170 #size-cells = <1>;
0171 reg = <0xe0100 0x60>;
0172 ranges = <0x0 0xe0100 0x60>;
0173 device_type = "par_io";
0174 num-ports = <3>;
0175 pio1: ucc_pin@1 {
0176 pio-map = <
0177 /* port pin dir open_drain assignment has_irq */
0178 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0179 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
0180 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
0181 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
0182 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
0183 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
0184 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
0185 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
0186 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
0187 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
0188 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
0189 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
0190 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
0191 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
0192 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
0193 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
0194 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
0195 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
0196 };
0197
0198 pio2: ucc_pin@2 {
0199 pio-map = <
0200 /* port pin dir open_drain assignment has_irq */
0201 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0202 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
0203 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
0204 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
0205 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
0206 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
0207 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
0208 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
0209 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
0210 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
0211 };
0212
0213 pio3: ucc_pin@3 {
0214 pio-map = <
0215 /* port pin dir open_drain assignment has_irq */
0216 0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
0217 0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/
0218 0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/
0219 0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/
0220 0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
0221 };
0222
0223 pio4: ucc_pin@4 {
0224 pio-map = <
0225 /* port pin dir open_drain assignment has_irq */
0226 0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
0227 0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/
0228 0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/
0229 0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/
0230 0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/
0231 };
0232 };
0233 };
0234
0235 &qe {
0236 enet3: ucc@2000 {
0237 device_type = "network";
0238 compatible = "ucc_geth";
0239 rx-clock-name = "clk12";
0240 tx-clock-name = "clk9";
0241 pio-handle = <&pio1>;
0242 phy-handle = <&qe_phy0>;
0243 phy-connection-type = "mii";
0244 };
0245
0246 mdio@2120 {
0247 qe_phy0: ethernet-phy@18 {
0248 interrupt-parent = <&mpic>;
0249 interrupts = <4 1 0 0>;
0250 reg = <0x18>;
0251 device_type = "ethernet-phy";
0252 };
0253 qe_phy1: ethernet-phy@19 {
0254 interrupt-parent = <&mpic>;
0255 interrupts = <5 1 0 0>;
0256 reg = <0x19>;
0257 device_type = "ethernet-phy";
0258 };
0259 tbi-phy@11 {
0260 reg = <0x11>;
0261 device_type = "tbi-phy";
0262 };
0263 };
0264
0265 enet4: ucc@2400 {
0266 device_type = "network";
0267 compatible = "ucc_geth";
0268 rx-clock-name = "none";
0269 tx-clock-name = "clk13";
0270 pio-handle = <&pio2>;
0271 phy-handle = <&qe_phy1>;
0272 phy-connection-type = "rmii";
0273 };
0274
0275 serial2: ucc@2600 {
0276 device_type = "serial";
0277 compatible = "ucc_uart";
0278 port-number = <0>;
0279 rx-clock-name = "brg6";
0280 tx-clock-name = "brg6";
0281 pio-handle = <&pio3>;
0282 };
0283
0284 serial3: ucc@2200 {
0285 device_type = "serial";
0286 compatible = "ucc_uart";
0287 port-number = <1>;
0288 rx-clock-name = "brg2";
0289 tx-clock-name = "brg2";
0290 pio-handle = <&pio4>;
0291 };
0292 };
