0001 /*
0002 * P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
0003 *
0004 * Copyright 2011 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 &lbc {
0036 nor@0,0 {
0037 #address-cells = <1>;
0038 #size-cells = <1>;
0039 compatible = "cfi-flash";
0040 reg = <0x0 0x0 0x1000000>;
0041 bank-width = <2>;
0042 device-width = <1>;
0043
0044 partition@0 {
0045 /* This location must not be altered */
0046 /* 256KB for Vitesse 7385 Switch firmware */
0047 reg = <0x0 0x00040000>;
0048 label = "NOR Vitesse-7385 Firmware";
0049 read-only;
0050 };
0051
0052 partition@40000 {
0053 /* 256KB for DTB Image */
0054 reg = <0x00040000 0x00040000>;
0055 label = "NOR DTB Image";
0056 };
0057
0058 partition@80000 {
0059 /* 3.5 MB for Linux Kernel Image */
0060 reg = <0x00080000 0x00380000>;
0061 label = "NOR Linux Kernel Image";
0062 };
0063
0064 partition@400000 {
0065 /* 11MB for JFFS2 based Root file System */
0066 reg = <0x00400000 0x00b00000>;
0067 label = "NOR JFFS2 Root File System";
0068 };
0069
0070 partition@f00000 {
0071 /* This location must not be altered */
0072 /* 512KB for u-boot Bootloader Image */
0073 /* 512KB for u-boot Environment Variables */
0074 reg = <0x00f00000 0x00100000>;
0075 label = "NOR U-Boot Image";
0076 read-only;
0077 };
0078 };
0079
0080 nand@1,0 {
0081 #address-cells = <1>;
0082 #size-cells = <1>;
0083 compatible = "fsl,p1025-fcm-nand",
0084 "fsl,elbc-fcm-nand";
0085 reg = <0x1 0x0 0x40000>;
0086
0087 partition@0 {
0088 /* This location must not be altered */
0089 /* 1MB for u-boot Bootloader Image */
0090 reg = <0x0 0x00100000>;
0091 label = "NAND U-Boot Image";
0092 read-only;
0093 };
0094
0095 partition@100000 {
0096 /* 1MB for DTB Image */
0097 reg = <0x00100000 0x00100000>;
0098 label = "NAND DTB Image";
0099 };
0100
0101 partition@200000 {
0102 /* 4MB for Linux Kernel Image */
0103 reg = <0x00200000 0x00400000>;
0104 label = "NAND Linux Kernel Image";
0105 };
0106
0107 partition@600000 {
0108 /* 4MB for Compressed Root file System Image */
0109 reg = <0x00600000 0x00400000>;
0110 label = "NAND Compressed RFS Image";
0111 };
0112
0113 partition@a00000 {
0114 /* 7MB for JFFS2 based Root file System */
0115 reg = <0x00a00000 0x00700000>;
0116 label = "NAND JFFS2 Root File System";
0117 };
0118
0119 partition@1100000 {
0120 /* 15MB for JFFS2 based Root file System */
0121 reg = <0x01100000 0x00f00000>;
0122 label = "NAND Writable User area";
0123 };
0124 };
0125
0126 };
0127
0128 &soc {
0129 i2c@3000 {
0130 rtc@68 {
0131 compatible = "dallas,ds1339";
0132 reg = <0x68>;
0133 };
0134 };
0135
0136 spi@7000 {
0137 flash@0 {
0138 #address-cells = <1>;
0139 #size-cells = <1>;
0140 compatible = "spansion,s25sl12801", "jedec,spi-nor";
0141 reg = <0>;
0142 spi-max-frequency = <40000000>; /* input clock */
0143
0144 partition@u-boot {
0145 /* 512KB for u-boot Bootloader Image */
0146 reg = <0x0 0x00080000>;
0147 label = "u-boot";
0148 read-only;
0149 };
0150
0151 partition@dtb {
0152 /* 512KB for DTB Image */
0153 reg = <0x00080000 0x00080000>;
0154 label = "dtb";
0155 };
0156
0157 partition@kernel {
0158 /* 4MB for Linux Kernel Image */
0159 reg = <0x00100000 0x00400000>;
0160 label = "kernel";
0161 };
0162
0163 partition@fs {
0164 /* 4MB for Compressed RFS Image */
0165 reg = <0x00500000 0x00400000>;
0166 label = "file system";
0167 };
0168
0169 partition@jffs-fs {
0170 /* 7MB for JFFS2 based RFS */
0171 reg = <0x00900000 0x00700000>;
0172 label = "file system jffs2";
0173 };
0174 };
0175 };
0176
0177 usb@22000 {
0178 phy_type = "ulpi";
0179 };
0180
0181 /* USB2 is shared with localbus, so it must be disabled
0182 by default. We can't put 'status = "disabled";' here
0183 since U-Boot doesn't clear the status property when
0184 it enables USB2. OTOH, U-Boot does create a new node
0185 when there isn't any. So, just comment it out.
0186 usb@23000 {
0187 phy_type = "ulpi";
0188 };
0189 */
0190
0191 mdio@24000 {
0192 phy0: ethernet-phy@0 {
0193 interrupt-parent = <&mpic>;
0194 interrupts = <3 1>;
0195 reg = <0x0>;
0196 };
0197
0198 phy1: ethernet-phy@1 {
0199 interrupt-parent = <&mpic>;
0200 interrupts = <2 1>;
0201 reg = <0x1>;
0202 };
0203
0204 tbi0: tbi-phy@11 {
0205 reg = <0x11>;
0206 device_type = "tbi-phy";
0207 };
0208 };
0209
0210 mdio@25000 {
0211 tbi1: tbi-phy@11 {
0212 reg = <0x11>;
0213 device_type = "tbi-phy";
0214 };
0215 };
0216
0217 mdio@26000 {
0218 tbi2: tbi-phy@11 {
0219 reg = <0x11>;
0220 device_type = "tbi-phy";
0221 };
0222 };
0223
0224 enet0: ethernet@b0000 {
0225 fixed-link = <1 1 1000 0 0>;
0226 phy-connection-type = "rgmii-id";
0227
0228 };
0229
0230 enet1: ethernet@b1000 {
0231 phy-handle = <&phy0>;
0232 tbi-handle = <&tbi1>;
0233 phy-connection-type = "sgmii";
0234 };
0235
0236 enet2: ethernet@b2000 {
0237 phy-handle = <&phy1>;
0238 phy-connection-type = "rgmii-id";
0239 };
0240
0241 par_io@e0100 {
0242 #address-cells = <1>;
0243 #size-cells = <1>;
0244 reg = <0xe0100 0x60>;
0245 ranges = <0x0 0xe0100 0x60>;
0246 device_type = "par_io";
0247 num-ports = <3>;
0248 pio1: ucc_pin@1 {
0249 pio-map = <
0250 /* port pin dir open_drain assignment has_irq */
0251 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0252 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
0253 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
0254 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
0255 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
0256 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
0257 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
0258 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
0259 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
0260 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
0261 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
0262 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
0263 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
0264 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
0265 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
0266 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
0267 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
0268 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
0269 };
0270
0271 pio2: ucc_pin@2 {
0272 pio-map = <
0273 /* port pin dir open_drain assignment has_irq */
0274 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0275 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
0276 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
0277 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
0278 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
0279 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
0280 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
0281 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
0282 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
0283 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
0284 };
0285
0286 pio3: ucc_pin@3 {
0287 pio-map = <
0288 /* port pin dir open_drain assignment has_irq */
0289 0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
0290 0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/
0291 0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/
0292 0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/
0293 0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
0294 };
0295
0296 pio4: ucc_pin@4 {
0297 pio-map = <
0298 /* port pin dir open_drain assignment has_irq */
0299 0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
0300 0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/
0301 0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/
0302 0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/
0303 0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/
0304 };
0305 };
0306 };
0307
0308 &qe {
0309 serial2: ucc@2600 {
0310 device_type = "serial";
0311 compatible = "ucc_uart";
0312 port-number = <0>;
0313 rx-clock-name = "brg6";
0314 tx-clock-name = "brg6";
0315 pio-handle = <&pio3>;
0316 };
0317
0318 serial3: ucc@2200 {
0319 device_type = "serial";
0320 compatible = "ucc_uart";
0321 port-number = <1>;
0322 rx-clock-name = "brg2";
0323 tx-clock-name = "brg2";
0324 pio-handle = <&pio4>;
0325 };
0326 };
