0001 /*
0002 * P1021/P1012 Silicon/SoC Device Tree Source (post include)
0003 *
0004 * Copyright 2011-2012 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 &lbc {
0036 #address-cells = <2>;
0037 #size-cells = <1>;
0038 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
0039 interrupts = <19 2 0 0>,
0040 <16 2 0 0>;
0041 };
0042
0043 /* controller at 0x9000 */
0044 &pci0 {
0045 compatible = "fsl,mpc8548-pcie";
0046 device_type = "pci";
0047 #size-cells = <2>;
0048 #address-cells = <3>;
0049 bus-range = <0 255>;
0050 clock-frequency = <33333333>;
0051 interrupts = <16 2 0 0>;
0052
0053 pcie@0 {
0054 reg = <0 0 0 0 0>;
0055 #interrupt-cells = <1>;
0056 #size-cells = <2>;
0057 #address-cells = <3>;
0058 device_type = "pci";
0059 interrupts = <16 2 0 0>;
0060 interrupt-map-mask = <0xf800 0 0 7>;
0061 interrupt-map = <
0062 /* IDSEL 0x0 */
0063 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
0064 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
0065 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
0066 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
0067 >;
0068 };
0069 };
0070
0071 /* controller at 0xa000 */
0072 &pci1 {
0073 compatible = "fsl,mpc8548-pcie";
0074 device_type = "pci";
0075 #size-cells = <2>;
0076 #address-cells = <3>;
0077 bus-range = <0 255>;
0078 clock-frequency = <33333333>;
0079 interrupts = <16 2 0 0>;
0080
0081 pcie@0 {
0082 reg = <0 0 0 0 0>;
0083 #interrupt-cells = <1>;
0084 #size-cells = <2>;
0085 #address-cells = <3>;
0086 device_type = "pci";
0087 interrupts = <16 2 0 0>;
0088 interrupt-map-mask = <0xf800 0 0 7>;
0089
0090 interrupt-map = <
0091 /* IDSEL 0x0 */
0092 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
0093 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
0094 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
0095 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
0096 >;
0097 };
0098 };
0099
0100 &soc {
0101 #address-cells = <1>;
0102 #size-cells = <1>;
0103 device_type = "soc";
0104 compatible = "fsl,p1021-immr", "simple-bus";
0105 bus-frequency = <0>; // Filled out by uboot.
0106
0107 ecm-law@0 {
0108 compatible = "fsl,ecm-law";
0109 reg = <0x0 0x1000>;
0110 fsl,num-laws = <12>;
0111 };
0112
0113 ecm@1000 {
0114 compatible = "fsl,p1021-ecm", "fsl,ecm";
0115 reg = <0x1000 0x1000>;
0116 interrupts = <16 2 0 0>;
0117 };
0118
0119 memory-controller@2000 {
0120 compatible = "fsl,p1021-memory-controller";
0121 reg = <0x2000 0x1000>;
0122 interrupts = <16 2 0 0>;
0123 };
0124
0125 /include/ "pq3-i2c-0.dtsi"
0126 /include/ "pq3-i2c-1.dtsi"
0127 /include/ "pq3-duart-0.dtsi"
0128
0129 /include/ "pq3-espi-0.dtsi"
0130 spi@7000 {
0131 fsl,espi-num-chipselects = <4>;
0132 };
0133
0134 /include/ "pq3-gpio-0.dtsi"
0135
0136 L2: l2-cache-controller@20000 {
0137 compatible = "fsl,p1021-l2-cache-controller";
0138 reg = <0x20000 0x1000>;
0139 cache-line-size = <32>; // 32 bytes
0140 cache-size = <0x40000>; // L2,256K
0141 interrupts = <16 2 0 0>;
0142 };
0143
0144 /include/ "pq3-dma-0.dtsi"
0145 /include/ "pq3-usb2-dr-0.dtsi"
0146 usb@22000 {
0147 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
0148 };
0149
0150 /include/ "pq3-esdhc-0.dtsi"
0151 sdhc@2e000 {
0152 sdhci,auto-cmd12;
0153 };
0154
0155 /include/ "pq3-sec3.3-0.dtsi"
0156
0157 /include/ "pq3-mpic.dtsi"
0158 /include/ "pq3-mpic-timer-B.dtsi"
0159
0160 /include/ "pq3-etsec2-0.dtsi"
0161 enet0: enet0_grp2: ethernet@b0000 {
0162 };
0163
0164 /include/ "pq3-etsec2-1.dtsi"
0165 enet1: enet1_grp2: ethernet@b1000 {
0166 };
0167
0168 /include/ "pq3-etsec2-2.dtsi"
0169 enet2: enet2_grp2: ethernet@b2000 {
0170 };
0171
0172 global-utilities@e0000 {
0173 compatible = "fsl,p1021-guts";
0174 reg = <0xe0000 0x1000>;
0175 fsl,has-rstcr;
0176 };
0177 };
0178
0179 &qe {
0180 #address-cells = <1>;
0181 #size-cells = <1>;
0182 device_type = "qe";
0183 compatible = "fsl,qe";
0184 fsl,qe-num-riscs = <1>;
0185 fsl,qe-num-snums = <28>;
0186
0187 qeic: interrupt-controller@80 {
0188 interrupt-controller;
0189 compatible = "fsl,qe-ic";
0190 #address-cells = <0>;
0191 #interrupt-cells = <1>;
0192 reg = <0x80 0x80>;
0193 interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44
0194 };
0195
0196 ucc@2000 {
0197 cell-index = <1>;
0198 reg = <0x2000 0x200>;
0199 interrupts = <32>;
0200 interrupt-parent = <&qeic>;
0201 };
0202
0203 mdio@2120 {
0204 #address-cells = <1>;
0205 #size-cells = <0>;
0206 reg = <0x2120 0x18>;
0207 compatible = "fsl,ucc-mdio";
0208 };
0209
0210 ucc@2400 {
0211 cell-index = <5>;
0212 reg = <0x2400 0x200>;
0213 interrupts = <40>;
0214 interrupt-parent = <&qeic>;
0215 };
0216
0217 ucc@2600 {
0218 cell-index = <7>;
0219 reg = <0x2600 0x200>;
0220 interrupts = <42>;
0221 interrupt-parent = <&qeic>;
0222 };
0223
0224 ucc@2200 {
0225 cell-index = <3>;
0226 reg = <0x2200 0x200>;
0227 interrupts = <34>;
0228 interrupt-parent = <&qeic>;
0229 };
0230
0231 muram@10000 {
0232 #address-cells = <1>;
0233 #size-cells = <1>;
0234 compatible = "fsl,qe-muram", "fsl,cpm-muram";
0235 ranges = <0x0 0x10000 0x6000>;
0236
0237 data-only@0 {
0238 compatible = "fsl,qe-muram-data",
0239 "fsl,cpm-muram-data";
0240 reg = <0x0 0x6000>;
0241 };
0242 };
0243 };
0244
0245 /include/ "pq3-etsec2-grp2-0.dtsi"
0246 /include/ "pq3-etsec2-grp2-1.dtsi"
0247 /include/ "pq3-etsec2-grp2-2.dtsi"
