0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8641 HPCN Device Tree Source
0004 *
0005 * Copyright 2006 Freescale Semiconductor Inc.
0006 */
0007
0008 /include/ "mpc8641si-pre.dtsi"
0009
0010 / {
0011 model = "MPC8641HPCN";
0012 compatible = "fsl,mpc8641hpcn";
0013
0014 memory {
0015 device_type = "memory";
0016 reg = <0x00000000 0x40000000>; // 1G at 0x0
0017 };
0018
0019 lbc: localbus@ffe05000 {
0020 reg = <0xffe05000 0x1000>;
0021
0022 ranges = <0 0 0xef800000 0x00800000
0023 2 0 0xffdf8000 0x00008000
0024 3 0 0xffdf0000 0x00008000>;
0025
0026 flash@0,0 {
0027 compatible = "cfi-flash";
0028 reg = <0 0 0x00800000>;
0029 bank-width = <2>;
0030 device-width = <2>;
0031 #address-cells = <1>;
0032 #size-cells = <1>;
0033 partition@0 {
0034 label = "kernel";
0035 reg = <0x00000000 0x00300000>;
0036 };
0037 partition@300000 {
0038 label = "firmware b";
0039 reg = <0x00300000 0x00100000>;
0040 read-only;
0041 };
0042 partition@400000 {
0043 label = "fs";
0044 reg = <0x00400000 0x00300000>;
0045 };
0046 partition@700000 {
0047 label = "firmware a";
0048 reg = <0x00700000 0x00100000>;
0049 read-only;
0050 };
0051 };
0052 };
0053
0054 soc: soc8641@ffe00000 {
0055 ranges = <0x00000000 0xffe00000 0x00100000>;
0056
0057 enet0: ethernet@24000 {
0058 tbi-handle = <&tbi0>;
0059 phy-handle = <&phy0>;
0060 phy-connection-type = "rgmii-id";
0061 };
0062
0063 mdio@24520 {
0064 phy0: ethernet-phy@0 {
0065 interrupts = <10 1 0 0>;
0066 reg = <0>;
0067 };
0068 phy1: ethernet-phy@1 {
0069 interrupts = <10 1 0 0>;
0070 reg = <1>;
0071 };
0072 phy2: ethernet-phy@2 {
0073 interrupts = <10 1 0 0>;
0074 reg = <2>;
0075 };
0076 phy3: ethernet-phy@3 {
0077 interrupts = <10 1 0 0>;
0078 reg = <3>;
0079 };
0080 tbi0: tbi-phy@11 {
0081 reg = <0x11>;
0082 device_type = "tbi-phy";
0083 };
0084 };
0085
0086 enet1: ethernet@25000 {
0087 tbi-handle = <&tbi1>;
0088 phy-handle = <&phy1>;
0089 phy-connection-type = "rgmii-id";
0090 };
0091
0092 mdio@25520 {
0093 tbi1: tbi-phy@11 {
0094 reg = <0x11>;
0095 device_type = "tbi-phy";
0096 };
0097 };
0098
0099 enet2: ethernet@26000 {
0100 tbi-handle = <&tbi2>;
0101 phy-handle = <&phy2>;
0102 phy-connection-type = "rgmii-id";
0103 };
0104
0105 mdio@26520 {
0106 tbi2: tbi-phy@11 {
0107 reg = <0x11>;
0108 device_type = "tbi-phy";
0109 };
0110 };
0111
0112 enet3: ethernet@27000 {
0113 tbi-handle = <&tbi3>;
0114 phy-handle = <&phy3>;
0115 phy-connection-type = "rgmii-id";
0116 };
0117
0118 mdio@27520 {
0119 tbi3: tbi-phy@11 {
0120 reg = <0x11>;
0121 device_type = "tbi-phy";
0122 };
0123 };
0124
0125 rmu: rmu@d3000 {
0126 #address-cells = <1>;
0127 #size-cells = <1>;
0128 compatible = "fsl,srio-rmu";
0129 reg = <0xd3000 0x500>;
0130 ranges = <0x0 0xd3000 0x500>;
0131
0132 message-unit@0 {
0133 compatible = "fsl,srio-msg-unit";
0134 reg = <0x0 0x100>;
0135 interrupts = <
0136 53 2 0 0 /* msg1_tx_irq */
0137 54 2 0 0>;/* msg1_rx_irq */
0138 };
0139 message-unit@100 {
0140 compatible = "fsl,srio-msg-unit";
0141 reg = <0x100 0x100>;
0142 interrupts = <
0143 55 2 0 0 /* msg2_tx_irq */
0144 56 2 0 0>;/* msg2_rx_irq */
0145 };
0146 doorbell-unit@400 {
0147 compatible = "fsl,srio-dbell-unit";
0148 reg = <0x400 0x80>;
0149 interrupts = <
0150 49 2 0 0 /* bell_outb_irq */
0151 50 2 0 0>;/* bell_inb_irq */
0152 };
0153 port-write-unit@4e0 {
0154 compatible = "fsl,srio-port-write-unit";
0155 reg = <0x4e0 0x20>;
0156 interrupts = <48 2 0 0>;
0157 };
0158 };
0159 };
0160
0161 pci0: pcie@ffe08000 {
0162 reg = <0xffe08000 0x1000>;
0163 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0164 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
0165 interrupt-map-mask = <0xff00 0 0 7>;
0166 interrupt-map = <
0167 /* IDSEL 0x11 func 0 - PCI slot 1 */
0168 0x8800 0 0 1 &mpic 2 1 0 0
0169 0x8800 0 0 2 &mpic 3 1 0 0
0170 0x8800 0 0 3 &mpic 4 1 0 0
0171 0x8800 0 0 4 &mpic 1 1 0 0
0172
0173 /* IDSEL 0x11 func 1 - PCI slot 1 */
0174 0x8900 0 0 1 &mpic 2 1 0 0
0175 0x8900 0 0 2 &mpic 3 1 0 0
0176 0x8900 0 0 3 &mpic 4 1 0 0
0177 0x8900 0 0 4 &mpic 1 1 0 0
0178
0179 /* IDSEL 0x11 func 2 - PCI slot 1 */
0180 0x8a00 0 0 1 &mpic 2 1 0 0
0181 0x8a00 0 0 2 &mpic 3 1 0 0
0182 0x8a00 0 0 3 &mpic 4 1 0 0
0183 0x8a00 0 0 4 &mpic 1 1 0 0
0184
0185 /* IDSEL 0x11 func 3 - PCI slot 1 */
0186 0x8b00 0 0 1 &mpic 2 1 0 0
0187 0x8b00 0 0 2 &mpic 3 1 0 0
0188 0x8b00 0 0 3 &mpic 4 1 0 0
0189 0x8b00 0 0 4 &mpic 1 1 0 0
0190
0191 /* IDSEL 0x11 func 4 - PCI slot 1 */
0192 0x8c00 0 0 1 &mpic 2 1 0 0
0193 0x8c00 0 0 2 &mpic 3 1 0 0
0194 0x8c00 0 0 3 &mpic 4 1 0 0
0195 0x8c00 0 0 4 &mpic 1 1 0 0
0196
0197 /* IDSEL 0x11 func 5 - PCI slot 1 */
0198 0x8d00 0 0 1 &mpic 2 1 0 0
0199 0x8d00 0 0 2 &mpic 3 1 0 0
0200 0x8d00 0 0 3 &mpic 4 1 0 0
0201 0x8d00 0 0 4 &mpic 1 1 0 0
0202
0203 /* IDSEL 0x11 func 6 - PCI slot 1 */
0204 0x8e00 0 0 1 &mpic 2 1 0 0
0205 0x8e00 0 0 2 &mpic 3 1 0 0
0206 0x8e00 0 0 3 &mpic 4 1 0 0
0207 0x8e00 0 0 4 &mpic 1 1 0 0
0208
0209 /* IDSEL 0x11 func 7 - PCI slot 1 */
0210 0x8f00 0 0 1 &mpic 2 1 0 0
0211 0x8f00 0 0 2 &mpic 3 1 0 0
0212 0x8f00 0 0 3 &mpic 4 1 0 0
0213 0x8f00 0 0 4 &mpic 1 1 0 0
0214
0215 /* IDSEL 0x12 func 0 - PCI slot 2 */
0216 0x9000 0 0 1 &mpic 3 1 0 0
0217 0x9000 0 0 2 &mpic 4 1 0 0
0218 0x9000 0 0 3 &mpic 1 1 0 0
0219 0x9000 0 0 4 &mpic 2 1 0 0
0220
0221 /* IDSEL 0x12 func 1 - PCI slot 2 */
0222 0x9100 0 0 1 &mpic 3 1 0 0
0223 0x9100 0 0 2 &mpic 4 1 0 0
0224 0x9100 0 0 3 &mpic 1 1 0 0
0225 0x9100 0 0 4 &mpic 2 1 0 0
0226
0227 /* IDSEL 0x12 func 2 - PCI slot 2 */
0228 0x9200 0 0 1 &mpic 3 1 0 0
0229 0x9200 0 0 2 &mpic 4 1 0 0
0230 0x9200 0 0 3 &mpic 1 1 0 0
0231 0x9200 0 0 4 &mpic 2 1 0 0
0232
0233 /* IDSEL 0x12 func 3 - PCI slot 2 */
0234 0x9300 0 0 1 &mpic 3 1 0 0
0235 0x9300 0 0 2 &mpic 4 1 0 0
0236 0x9300 0 0 3 &mpic 1 1 0 0
0237 0x9300 0 0 4 &mpic 2 1 0 0
0238
0239 /* IDSEL 0x12 func 4 - PCI slot 2 */
0240 0x9400 0 0 1 &mpic 3 1 0 0
0241 0x9400 0 0 2 &mpic 4 1 0 0
0242 0x9400 0 0 3 &mpic 1 1 0 0
0243 0x9400 0 0 4 &mpic 2 1 0 0
0244
0245 /* IDSEL 0x12 func 5 - PCI slot 2 */
0246 0x9500 0 0 1 &mpic 3 1 0 0
0247 0x9500 0 0 2 &mpic 4 1 0 0
0248 0x9500 0 0 3 &mpic 1 1 0 0
0249 0x9500 0 0 4 &mpic 2 1 0 0
0250
0251 /* IDSEL 0x12 func 6 - PCI slot 2 */
0252 0x9600 0 0 1 &mpic 3 1 0 0
0253 0x9600 0 0 2 &mpic 4 1 0 0
0254 0x9600 0 0 3 &mpic 1 1 0 0
0255 0x9600 0 0 4 &mpic 2 1 0 0
0256
0257 /* IDSEL 0x12 func 7 - PCI slot 2 */
0258 0x9700 0 0 1 &mpic 3 1 0 0
0259 0x9700 0 0 2 &mpic 4 1 0 0
0260 0x9700 0 0 3 &mpic 1 1 0 0
0261 0x9700 0 0 4 &mpic 2 1 0 0
0262
0263 // IDSEL 0x1c USB
0264 0xe000 0 0 1 &i8259 12 2
0265 0xe100 0 0 2 &i8259 9 2
0266 0xe200 0 0 3 &i8259 10 2
0267 0xe300 0 0 4 &i8259 11 2
0268
0269 // IDSEL 0x1d Audio
0270 0xe800 0 0 1 &i8259 6 2
0271
0272 // IDSEL 0x1e Legacy
0273 0xf000 0 0 1 &i8259 7 2
0274 0xf100 0 0 1 &i8259 7 2
0275
0276 // IDSEL 0x1f IDE/SATA
0277 0xf800 0 0 1 &i8259 14 2
0278 0xf900 0 0 1 &i8259 5 2
0279 >;
0280
0281 pcie@0 {
0282 ranges = <0x02000000 0x0 0x80000000
0283 0x02000000 0x0 0x80000000
0284 0x0 0x20000000
0285
0286 0x01000000 0x0 0x00000000
0287 0x01000000 0x0 0x00000000
0288 0x0 0x00010000>;
0289 uli1575@0 {
0290 reg = <0 0 0 0 0>;
0291 #size-cells = <2>;
0292 #address-cells = <3>;
0293 ranges = <0x02000000 0x0 0x80000000
0294 0x02000000 0x0 0x80000000
0295 0x0 0x20000000
0296 0x01000000 0x0 0x00000000
0297 0x01000000 0x0 0x00000000
0298 0x0 0x00010000>;
0299 isa@1e {
0300 device_type = "isa";
0301 #size-cells = <1>;
0302 #address-cells = <2>;
0303 reg = <0xf000 0 0 0 0>;
0304 ranges = <1 0 0x01000000 0 0
0305 0x00001000>;
0306 interrupt-parent = <&i8259>;
0307
0308 i8259: interrupt-controller@20 {
0309 reg = <1 0x20 2
0310 1 0xa0 2
0311 1 0x4d0 2>;
0312 interrupt-controller;
0313 device_type = "interrupt-controller";
0314 #address-cells = <0>;
0315 #interrupt-cells = <2>;
0316 compatible = "chrp,iic";
0317 interrupts = <9 2 0 0>;
0318 };
0319
0320 i8042@60 {
0321 #size-cells = <0>;
0322 #address-cells = <1>;
0323 reg = <1 0x60 1 1 0x64 1>;
0324 interrupts = <1 3 12 3>;
0325 interrupt-parent = <&i8259>;
0326
0327 keyboard@0 {
0328 reg = <0>;
0329 compatible = "pnpPNP,303";
0330 };
0331
0332 mouse@1 {
0333 reg = <1>;
0334 compatible = "pnpPNP,f03";
0335 };
0336 };
0337
0338 rtc@70 {
0339 compatible =
0340 "pnpPNP,b00";
0341 reg = <1 0x70 2>;
0342 };
0343
0344 gpio@400 {
0345 reg = <1 0x400 0x80>;
0346 };
0347 };
0348 };
0349 };
0350
0351 };
0352
0353 pci1: pcie@ffe09000 {
0354 reg = <0xffe09000 0x1000>;
0355 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0356 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
0357
0358 pcie@0 {
0359 ranges = <0x02000000 0x0 0xa0000000
0360 0x02000000 0x0 0xa0000000
0361 0x0 0x20000000
0362
0363 0x01000000 0x0 0x00000000
0364 0x01000000 0x0 0x00000000
0365 0x0 0x00010000>;
0366 };
0367 };
0368 /*
0369 * Only one of Rapid IO or PCI can be present due to HW limitations and
0370 * due to the fact that the 2 now share address space in the new memory
0371 * map. The most likely case is that we have PCI, so comment out the
0372 * rapidio node. Leave it here for reference.
0373
0374 rapidio@ffec0000 {
0375 reg = <0xffec0000 0x11000>;
0376 compatible = "fsl,srio";
0377 interrupts = <48 2 0 0>;
0378 #address-cells = <2>;
0379 #size-cells = <2>;
0380 fsl,srio-rmu-handle = <&rmu>;
0381 ranges;
0382
0383 port1 {
0384 #address-cells = <2>;
0385 #size-cells = <2>;
0386 cell-index = <1>;
0387 ranges = <0 0 0x80000000 0 0x20000000>;
0388 };
0389 };
0390 */
0391
0392 };
0393
0394 /include/ "mpc8641si-post.dtsi"
