0001 /*
0002 * MPC8572 Silicon/SoC Device Tree Source (post include)
0003 *
0004 * Copyright 2011 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 &lbc {
0036 #address-cells = <2>;
0037 #size-cells = <1>;
0038 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
0039 interrupts = <19 2 0 0>;
0040 };
0041
0042 /* controller at 0x8000 */
0043 &pci0 {
0044 compatible = "fsl,mpc8548-pcie";
0045 device_type = "pci";
0046 #size-cells = <2>;
0047 #address-cells = <3>;
0048 bus-range = <0 255>;
0049 clock-frequency = <33333333>;
0050 interrupts = <24 2 0 0>;
0051
0052 pcie@0 {
0053 reg = <0 0 0 0 0>;
0054 #interrupt-cells = <1>;
0055 #size-cells = <2>;
0056 #address-cells = <3>;
0057 device_type = "pci";
0058 interrupts = <24 2 0 0>;
0059 interrupt-map-mask = <0xf800 0 0 7>;
0060
0061 interrupt-map = <
0062 /* IDSEL 0x0 */
0063 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
0064 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
0065 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
0066 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
0067 >;
0068 };
0069 };
0070
0071 /* controller at 0x9000 */
0072 &pci1 {
0073 compatible = "fsl,mpc8548-pcie";
0074 device_type = "pci";
0075 #size-cells = <2>;
0076 #address-cells = <3>;
0077 bus-range = <0 255>;
0078 clock-frequency = <33333333>;
0079 interrupts = <25 2 0 0>;
0080
0081 pcie@0 {
0082 reg = <0 0 0 0 0>;
0083 #interrupt-cells = <1>;
0084 #size-cells = <2>;
0085 #address-cells = <3>;
0086 device_type = "pci";
0087 interrupts = <25 2 0 0>;
0088 interrupt-map-mask = <0xf800 0 0 7>;
0089
0090 interrupt-map = <
0091 /* IDSEL 0x0 */
0092 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
0093 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
0094 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
0095 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
0096 >;
0097 };
0098 };
0099
0100 /* controller at 0xa000 */
0101 &pci2 {
0102 compatible = "fsl,mpc8548-pcie";
0103 device_type = "pci";
0104 #size-cells = <2>;
0105 #address-cells = <3>;
0106 bus-range = <0 255>;
0107 clock-frequency = <33333333>;
0108 interrupts = <26 2 0 0>;
0109
0110 pcie@0 {
0111 reg = <0 0 0 0 0>;
0112 #interrupt-cells = <1>;
0113 #size-cells = <2>;
0114 #address-cells = <3>;
0115 device_type = "pci";
0116 interrupts = <26 2 0 0>;
0117 interrupt-map-mask = <0xf800 0 0 7>;
0118 interrupt-map = <
0119 /* IDSEL 0x0 */
0120 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
0121 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
0122 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
0123 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
0124 >;
0125 };
0126 };
0127
0128 &soc {
0129 #address-cells = <1>;
0130 #size-cells = <1>;
0131 device_type = "soc";
0132 compatible = "fsl,mpc8572-immr", "simple-bus";
0133 bus-frequency = <0>; // Filled out by uboot.
0134
0135 ecm-law@0 {
0136 compatible = "fsl,ecm-law";
0137 reg = <0x0 0x1000>;
0138 fsl,num-laws = <12>;
0139 };
0140
0141 ecm@1000 {
0142 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
0143 reg = <0x1000 0x1000>;
0144 interrupts = <17 2 0 0>;
0145 };
0146
0147 memory-controller@2000 {
0148 compatible = "fsl,mpc8572-memory-controller";
0149 reg = <0x2000 0x1000>;
0150 interrupts = <18 2 0 0>;
0151 };
0152
0153 memory-controller@6000 {
0154 compatible = "fsl,mpc8572-memory-controller";
0155 reg = <0x6000 0x1000>;
0156 interrupts = <18 2 0 0>;
0157 };
0158
0159 /include/ "pq3-i2c-0.dtsi"
0160 /include/ "pq3-i2c-1.dtsi"
0161 /include/ "pq3-duart-0.dtsi"
0162 /include/ "pq3-dma-1.dtsi"
0163 /include/ "pq3-gpio-0.dtsi"
0164 gpio-controller@f000 {
0165 compatible = "fsl,mpc8572-gpio";
0166 };
0167
0168 L2: l2-cache-controller@20000 {
0169 compatible = "fsl,mpc8572-l2-cache-controller";
0170 reg = <0x20000 0x1000>;
0171 cache-line-size = <32>; // 32 bytes
0172 cache-size = <0x100000>; // L2,1M
0173 interrupts = <16 2 0 0>;
0174 };
0175
0176 /include/ "pq3-dma-0.dtsi"
0177 /include/ "pq3-etsec1-0.dtsi"
0178 /include/ "pq3-etsec1-timer-0.dtsi"
0179
0180 ptp_clock@24e00 {
0181 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
0182 };
0183
0184 /include/ "pq3-etsec1-1.dtsi"
0185 /include/ "pq3-etsec1-2.dtsi"
0186 /include/ "pq3-etsec1-3.dtsi"
0187 /include/ "pq3-sec3.0-0.dtsi"
0188 /include/ "pq3-mpic.dtsi"
0189 /include/ "pq3-mpic-timer-B.dtsi"
0190
0191 global-utilities@e0000 {
0192 compatible = "fsl,mpc8572-guts";
0193 reg = <0xe0000 0x1000>;
0194 fsl,has-rstcr;
0195 };
0196 };
