0001 /*
0002 * MPC8569 Silicon/SoC Device Tree Source (post include)
0003 *
0004 * Copyright 2011 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 &lbc {
0036 #address-cells = <2>;
0037 #size-cells = <1>;
0038 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
0039 interrupts = <19 2 0 0>;
0040 sleep = <&pmc 0x08000000>;
0041 };
0042
0043 /* controller at 0xa000 */
0044 &pci1 {
0045 compatible = "fsl,mpc8548-pcie";
0046 device_type = "pci";
0047 #size-cells = <2>;
0048 #address-cells = <3>;
0049 bus-range = <0 255>;
0050 clock-frequency = <33333333>;
0051 interrupts = <26 2 0 0>;
0052 sleep = <&pmc 0x20000000>;
0053
0054 pcie@0 {
0055 reg = <0 0 0 0 0>;
0056 #interrupt-cells = <1>;
0057 #size-cells = <2>;
0058 #address-cells = <3>;
0059 device_type = "pci";
0060 interrupts = <26 2 0 0>;
0061 interrupt-map-mask = <0xf800 0 0 7>;
0062 interrupt-map = <
0063 /* IDSEL 0x0 */
0064 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
0065 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
0066 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
0067 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
0068 >;
0069 };
0070 };
0071
0072 &rio {
0073 compatible = "fsl,srio";
0074 interrupts = <48 2 0 0>;
0075 #address-cells = <2>;
0076 #size-cells = <2>;
0077 fsl,srio-rmu-handle = <&rmu>;
0078 sleep = <&pmc 0x00080000>;
0079 ranges;
0080
0081 port1 {
0082 #address-cells = <2>;
0083 #size-cells = <2>;
0084 cell-index = <1>;
0085 };
0086
0087 port2 {
0088 #address-cells = <2>;
0089 #size-cells = <2>;
0090 cell-index = <2>;
0091 };
0092 };
0093
0094 &soc {
0095 #address-cells = <1>;
0096 #size-cells = <1>;
0097 device_type = "soc";
0098 compatible = "fsl,mpc8569-immr", "simple-bus";
0099 bus-frequency = <0>; // Filled out by uboot.
0100
0101 ecm-law@0 {
0102 compatible = "fsl,ecm-law";
0103 reg = <0x0 0x1000>;
0104 fsl,num-laws = <10>;
0105 };
0106
0107 ecm@1000 {
0108 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
0109 reg = <0x1000 0x1000>;
0110 interrupts = <17 2 0 0>;
0111 };
0112
0113 memory-controller@2000 {
0114 compatible = "fsl,mpc8569-memory-controller";
0115 reg = <0x2000 0x1000>;
0116 interrupts = <18 2 0 0>;
0117 };
0118
0119 i2c-sleep-nexus {
0120 #address-cells = <1>;
0121 #size-cells = <1>;
0122 compatible = "simple-bus";
0123 sleep = <&pmc 0x00000004>;
0124 ranges;
0125
0126 /include/ "pq3-i2c-0.dtsi"
0127 /include/ "pq3-i2c-1.dtsi"
0128
0129 };
0130
0131 duart-sleep-nexus {
0132 #address-cells = <1>;
0133 #size-cells = <1>;
0134 compatible = "simple-bus";
0135 sleep = <&pmc 0x00000002>;
0136 ranges;
0137
0138 /include/ "pq3-duart-0.dtsi"
0139
0140 };
0141
0142 L2: l2-cache-controller@20000 {
0143 compatible = "fsl,mpc8569-l2-cache-controller";
0144 reg = <0x20000 0x1000>;
0145 cache-line-size = <32>; // 32 bytes
0146 cache-size = <0x80000>; // L2, 512K
0147 interrupts = <16 2 0 0>;
0148 };
0149
0150 /include/ "pq3-dma-0.dtsi"
0151 /include/ "pq3-esdhc-0.dtsi"
0152 sdhc@2e000 {
0153 sleep = <&pmc 0x00200000>;
0154 };
0155
0156 par_io@e0100 {
0157 #address-cells = <1>;
0158 #size-cells = <1>;
0159 reg = <0xe0100 0x100>;
0160 ranges = <0x0 0xe0100 0x100>;
0161 device_type = "par_io";
0162 };
0163
0164 /include/ "pq3-sec3.1-0.dtsi"
0165 crypto@30000 {
0166 sleep = <&pmc 0x01000000>;
0167 };
0168
0169 /include/ "pq3-mpic.dtsi"
0170 /include/ "pq3-rmu-0.dtsi"
0171 rmu@d3000 {
0172 sleep = <&pmc 0x00040000>;
0173 };
0174
0175 global-utilities@e0000 {
0176 #address-cells = <1>;
0177 #size-cells = <1>;
0178 compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
0179 reg = <0xe0000 0x1000>;
0180 ranges = <0 0xe0000 0x1000>;
0181 fsl,has-rstcr;
0182
0183 pmc: power@70 {
0184 compatible = "fsl,mpc8569-pmc",
0185 "fsl,mpc8548-pmc";
0186 reg = <0x70 0x20>;
0187 };
0188 };
0189 };
0190
0191 &qe {
0192 #address-cells = <1>;
0193 #size-cells = <1>;
0194 device_type = "qe";
0195 compatible = "fsl,qe";
0196 sleep = <&pmc 0x00000800>;
0197 brg-frequency = <0>;
0198 bus-frequency = <0>;
0199 fsl,qe-num-riscs = <4>;
0200 fsl,qe-num-snums = <46>;
0201
0202 qeic: interrupt-controller@80 {
0203 interrupt-controller;
0204 compatible = "fsl,qe-ic";
0205 #address-cells = <0>;
0206 #interrupt-cells = <1>;
0207 reg = <0x80 0x80>;
0208 interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
0209 interrupt-parent = <&mpic>;
0210 };
0211
0212 timer@440 {
0213 compatible = "fsl,mpc8569-qe-gtm",
0214 "fsl,qe-gtm", "fsl,gtm";
0215 reg = <0x440 0x40>;
0216 interrupts = <12 13 14 15>;
0217 interrupt-parent = <&qeic>;
0218 /* Filled in by U-Boot */
0219 clock-frequency = <0>;
0220 };
0221
0222 spi@4c0 {
0223 #address-cells = <1>;
0224 #size-cells = <0>;
0225 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
0226 reg = <0x4c0 0x40>;
0227 cell-index = <0>;
0228 interrupts = <2>;
0229 interrupt-parent = <&qeic>;
0230 };
0231
0232 spi@500 {
0233 #address-cells = <1>;
0234 #size-cells = <0>;
0235 cell-index = <1>;
0236 compatible = "fsl,spi";
0237 reg = <0x500 0x40>;
0238 interrupts = <1>;
0239 interrupt-parent = <&qeic>;
0240 };
0241
0242 usb@6c0 {
0243 compatible = "fsl,mpc8569-qe-usb",
0244 "fsl,mpc8323-qe-usb";
0245 reg = <0x6c0 0x40 0x8b00 0x100>;
0246 interrupts = <11>;
0247 interrupt-parent = <&qeic>;
0248 };
0249
0250 ucc@2000 {
0251 cell-index = <1>;
0252 reg = <0x2000 0x200>;
0253 interrupts = <32>;
0254 interrupt-parent = <&qeic>;
0255 };
0256
0257 ucc@2200 {
0258 cell-index = <3>;
0259 reg = <0x2200 0x200>;
0260 interrupts = <34>;
0261 interrupt-parent = <&qeic>;
0262 };
0263
0264 ucc@3000 {
0265 cell-index = <2>;
0266 reg = <0x3000 0x200>;
0267 interrupts = <33>;
0268 interrupt-parent = <&qeic>;
0269 };
0270
0271 ucc@3200 {
0272 cell-index = <4>;
0273 reg = <0x3200 0x200>;
0274 interrupts = <35>;
0275 interrupt-parent = <&qeic>;
0276 };
0277
0278 ucc@3400 {
0279 cell-index = <6>;
0280 reg = <0x3400 0x200>;
0281 interrupts = <41>;
0282 interrupt-parent = <&qeic>;
0283 };
0284
0285 ucc@3600 {
0286 cell-index = <8>;
0287 reg = <0x3600 0x200>;
0288 interrupts = <43>;
0289 interrupt-parent = <&qeic>;
0290 };
0291
0292 muram@10000 {
0293 #address-cells = <1>;
0294 #size-cells = <1>;
0295 compatible = "fsl,qe-muram", "fsl,cpm-muram";
0296 ranges = <0x0 0x10000 0x20000>;
0297
0298 data-only@0 {
0299 compatible = "fsl,qe-muram-data",
0300 "fsl,cpm-muram-data";
0301 reg = <0x0 0x20000>;
0302 };
0303 };
0304 };
