0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8569E MDS Device Tree Source
0004 *
0005 * Copyright (C) 2009 Freescale Semiconductor Inc.
0006 */
0007
0008 /include/ "mpc8569si-pre.dtsi"
0009
0010 / {
0011 model = "MPC8569EMDS";
0012 compatible = "fsl,MPC8569EMDS";
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015 interrupt-parent = <&mpic>;
0016
0017 aliases {
0018 ethernet2 = &enet2;
0019 ethernet3 = &enet3;
0020 ethernet5 = &enet5;
0021 ethernet7 = &enet7;
0022 rapidio0 = &rio;
0023 };
0024
0025 memory {
0026 device_type = "memory";
0027 };
0028
0029 lbc: localbus@e0005000 {
0030 reg = <0x0 0xe0005000 0x0 0x1000>;
0031
0032 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
0033 0x1 0x0 0x0 0xf8000000 0x00008000
0034 0x2 0x0 0x0 0xf0000000 0x04000000
0035 0x3 0x0 0x0 0xfc000000 0x00008000
0036 0x4 0x0 0x0 0xf8008000 0x00008000
0037 0x5 0x0 0x0 0xf8010000 0x00008000>;
0038
0039 nor@0,0 {
0040 #address-cells = <1>;
0041 #size-cells = <1>;
0042 compatible = "cfi-flash";
0043 reg = <0x0 0x0 0x02000000>;
0044 bank-width = <1>;
0045 device-width = <1>;
0046 partition@0 {
0047 label = "ramdisk";
0048 reg = <0x00000000 0x01c00000>;
0049 };
0050 partition@1c00000 {
0051 label = "kernel";
0052 reg = <0x01c00000 0x002e0000>;
0053 };
0054 partition@1ee0000 {
0055 label = "dtb";
0056 reg = <0x01ee0000 0x00020000>;
0057 };
0058 partition@1f00000 {
0059 label = "firmware";
0060 reg = <0x01f00000 0x00080000>;
0061 read-only;
0062 };
0063 partition@1f80000 {
0064 label = "u-boot";
0065 reg = <0x01f80000 0x00080000>;
0066 read-only;
0067 };
0068 };
0069
0070 bcsr@1,0 {
0071 #address-cells = <1>;
0072 #size-cells = <1>;
0073 compatible = "fsl,mpc8569mds-bcsr";
0074 reg = <1 0 0x8000>;
0075 ranges = <0 1 0 0x8000>;
0076
0077 bcsr17: gpio-controller@11 {
0078 #gpio-cells = <2>;
0079 compatible = "fsl,mpc8569mds-bcsr-gpio";
0080 reg = <0x11 0x1>;
0081 gpio-controller;
0082 };
0083 };
0084
0085 nand@3,0 {
0086 compatible = "fsl,mpc8569-fcm-nand",
0087 "fsl,elbc-fcm-nand";
0088 reg = <3 0 0x8000>;
0089 };
0090
0091 pib@4,0 {
0092 compatible = "fsl,mpc8569mds-pib";
0093 reg = <4 0 0x8000>;
0094 };
0095
0096 pib@5,0 {
0097 compatible = "fsl,mpc8569mds-pib";
0098 reg = <5 0 0x8000>;
0099 };
0100 };
0101
0102 soc: soc@e0000000 {
0103 ranges = <0x0 0x0 0xe0000000 0x100000>;
0104
0105 i2c-sleep-nexus {
0106 i2c@3000 {
0107 rtc@68 {
0108 compatible = "dallas,ds1374";
0109 reg = <0x68>;
0110 interrupts = <3 1 0 0>;
0111 };
0112 };
0113 };
0114
0115 sdhc@2e000 {
0116 status = "disabled";
0117 sdhci,1-bit-only;
0118 bus-width = <1>;
0119 };
0120
0121 par_io@e0100 {
0122 num-ports = <7>;
0123
0124 qe_pio_e: gpio-controller@80 {
0125 #gpio-cells = <2>;
0126 compatible = "fsl,mpc8569-qe-pario-bank",
0127 "fsl,mpc8323-qe-pario-bank";
0128 reg = <0x80 0x18>;
0129 gpio-controller;
0130 };
0131
0132 qe_pio_f: gpio-controller@a0 {
0133 #gpio-cells = <2>;
0134 compatible = "fsl,mpc8569-qe-pario-bank",
0135 "fsl,mpc8323-qe-pario-bank";
0136 reg = <0xa0 0x18>;
0137 gpio-controller;
0138 };
0139
0140 pio1: ucc_pin@1 {
0141 pio-map = <
0142 /* port pin dir open_drain assignment has_irq */
0143 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0144 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
0145 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
0146 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
0147 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
0148 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
0149 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
0150 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
0151 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
0152 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
0153 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
0154 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
0155 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
0156 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
0157 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
0158 };
0159
0160 pio2: ucc_pin@2 {
0161 pio-map = <
0162 /* port pin dir open_drain assignment has_irq */
0163 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0164 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
0165 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
0166 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
0167 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
0168 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
0169 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
0170 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
0171 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
0172 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
0173 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
0174 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
0175 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
0176 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
0177 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
0178 };
0179
0180 pio3: ucc_pin@3 {
0181 pio-map = <
0182 /* port pin dir open_drain assignment has_irq */
0183 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0184 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
0185 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
0186 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
0187 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
0188 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
0189 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
0190 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
0191 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
0192 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
0193 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
0194 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
0195 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
0196 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
0197 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
0198 };
0199
0200 pio4: ucc_pin@4 {
0201 pio-map = <
0202 /* port pin dir open_drain assignment has_irq */
0203 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0204 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
0205 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
0206 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
0207 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
0208 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
0209 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
0210 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
0211 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
0212 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
0213 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
0214 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
0215 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
0216 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
0217 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
0218 };
0219 };
0220 };
0221
0222 qe: qe@e0080000 {
0223 ranges = <0x0 0x0 0xe0080000 0x40000>;
0224 reg = <0x0 0xe0080000 0x0 0x480>;
0225
0226 spi@4c0 {
0227 gpios = <&qe_pio_e 30 0>;
0228 mode = "cpu-qe";
0229
0230 serial-flash@0 {
0231 compatible = "st,m25p40";
0232 reg = <0>;
0233 spi-max-frequency = <25000000>;
0234 };
0235 };
0236
0237 spi@500 {
0238 mode = "cpu";
0239 };
0240
0241 usb@6c0 {
0242 fsl,fullspeed-clock = "clk5";
0243 fsl,lowspeed-clock = "brg10";
0244 gpios = <&qe_pio_f 3 0 /* USBOE */
0245 &qe_pio_f 4 0 /* USBTP */
0246 &qe_pio_f 5 0 /* USBTN */
0247 &qe_pio_f 6 0 /* USBRP */
0248 &qe_pio_f 8 0 /* USBRN */
0249 &bcsr17 1 0 /* SPEED */
0250 &bcsr17 2 0>; /* POWER */
0251 };
0252
0253 enet0: ucc@2000 {
0254 device_type = "network";
0255 compatible = "ucc_geth";
0256 local-mac-address = [ 00 00 00 00 00 00 ];
0257 rx-clock-name = "none";
0258 tx-clock-name = "clk12";
0259 pio-handle = <&pio1>;
0260 tbi-handle = <&tbi1>;
0261 phy-handle = <&qe_phy0>;
0262 phy-connection-type = "rgmii-id";
0263 };
0264
0265 mdio@2120 {
0266 #address-cells = <1>;
0267 #size-cells = <0>;
0268 reg = <0x2120 0x18>;
0269 compatible = "fsl,ucc-mdio";
0270
0271 qe_phy0: ethernet-phy@7 {
0272 interrupt-parent = <&mpic>;
0273 interrupts = <1 1 0 0>;
0274 reg = <0x7>;
0275 };
0276 qe_phy1: ethernet-phy@1 {
0277 interrupt-parent = <&mpic>;
0278 interrupts = <2 1 0 0>;
0279 reg = <0x1>;
0280 };
0281 qe_phy2: ethernet-phy@2 {
0282 interrupt-parent = <&mpic>;
0283 interrupts = <3 1 0 0>;
0284 reg = <0x2>;
0285 };
0286 qe_phy3: ethernet-phy@3 {
0287 interrupt-parent = <&mpic>;
0288 interrupts = <4 1 0 0>;
0289 reg = <0x3>;
0290 };
0291 qe_phy5: ethernet-phy@4 {
0292 reg = <0x04>;
0293 };
0294 qe_phy7: ethernet-phy@6 {
0295 reg = <0x6>;
0296 };
0297 tbi1: tbi-phy@11 {
0298 reg = <0x11>;
0299 device_type = "tbi-phy";
0300 };
0301 };
0302 mdio@3520 {
0303 #address-cells = <1>;
0304 #size-cells = <0>;
0305 reg = <0x3520 0x18>;
0306 compatible = "fsl,ucc-mdio";
0307
0308 tbi6: tbi-phy@15 {
0309 reg = <0x15>;
0310 device_type = "tbi-phy";
0311 };
0312 };
0313 mdio@3720 {
0314 #address-cells = <1>;
0315 #size-cells = <0>;
0316 reg = <0x3720 0x38>;
0317 compatible = "fsl,ucc-mdio";
0318 tbi8: tbi-phy@17 {
0319 reg = <0x17>;
0320 device_type = "tbi-phy";
0321 };
0322 };
0323
0324 enet2: ucc@2200 {
0325 device_type = "network";
0326 compatible = "ucc_geth";
0327 local-mac-address = [ 00 00 00 00 00 00 ];
0328 rx-clock-name = "none";
0329 tx-clock-name = "clk12";
0330 pio-handle = <&pio3>;
0331 tbi-handle = <&tbi3>;
0332 phy-handle = <&qe_phy2>;
0333 phy-connection-type = "rgmii-id";
0334 };
0335
0336 mdio@2320 {
0337 #address-cells = <1>;
0338 #size-cells = <0>;
0339 reg = <0x2320 0x18>;
0340 compatible = "fsl,ucc-mdio";
0341 tbi3: tbi-phy@11 {
0342 reg = <0x11>;
0343 device_type = "tbi-phy";
0344 };
0345 };
0346
0347 enet1: ucc@3000 {
0348 device_type = "network";
0349 compatible = "ucc_geth";
0350 local-mac-address = [ 00 00 00 00 00 00 ];
0351 rx-clock-name = "none";
0352 tx-clock-name = "clk17";
0353 pio-handle = <&pio2>;
0354 tbi-handle = <&tbi2>;
0355 phy-handle = <&qe_phy1>;
0356 phy-connection-type = "rgmii-id";
0357 };
0358
0359 mdio@3120 {
0360 #address-cells = <1>;
0361 #size-cells = <0>;
0362 reg = <0x3120 0x18>;
0363 compatible = "fsl,ucc-mdio";
0364 tbi2: tbi-phy@11 {
0365 reg = <0x11>;
0366 device_type = "tbi-phy";
0367 };
0368 };
0369
0370 enet3: ucc@3200 {
0371 device_type = "network";
0372 compatible = "ucc_geth";
0373 local-mac-address = [ 00 00 00 00 00 00 ];
0374 rx-clock-name = "none";
0375 tx-clock-name = "clk17";
0376 pio-handle = <&pio4>;
0377 tbi-handle = <&tbi4>;
0378 phy-handle = <&qe_phy3>;
0379 phy-connection-type = "rgmii-id";
0380 };
0381
0382 mdio@3320 {
0383 #address-cells = <1>;
0384 #size-cells = <0>;
0385 reg = <0x3320 0x18>;
0386 compatible = "fsl,ucc-mdio";
0387 tbi4: tbi-phy@11 {
0388 reg = <0x11>;
0389 device_type = "tbi-phy";
0390 };
0391 };
0392
0393 enet5: ucc@3400 {
0394 device_type = "network";
0395 compatible = "ucc_geth";
0396 local-mac-address = [ 00 00 00 00 00 00 ];
0397 rx-clock-name = "none";
0398 tx-clock-name = "none";
0399 tbi-handle = <&tbi6>;
0400 phy-handle = <&qe_phy5>;
0401 phy-connection-type = "sgmii";
0402 };
0403
0404 enet7: ucc@3600 {
0405 device_type = "network";
0406 compatible = "ucc_geth";
0407 local-mac-address = [ 00 00 00 00 00 00 ];
0408 rx-clock-name = "none";
0409 tx-clock-name = "none";
0410 tbi-handle = <&tbi8>;
0411 phy-handle = <&qe_phy7>;
0412 phy-connection-type = "sgmii";
0413 };
0414 };
0415
0416 /* PCI Express */
0417 pci1: pcie@e000a000 {
0418 reg = <0x0 0xe000a000 0x0 0x1000>;
0419 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
0420 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>;
0421 pcie@0 {
0422 ranges = <0x2000000 0x0 0xa0000000
0423 0x2000000 0x0 0xa0000000
0424 0x0 0x10000000
0425
0426 0x1000000 0x0 0x0
0427 0x1000000 0x0 0x0
0428 0x0 0x800000>;
0429 };
0430 };
0431
0432 rio: rapidio@e00c00000 {
0433 reg = <0x0 0xe00c0000 0x0 0x20000>;
0434 port1 {
0435 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
0436 };
0437 port2 {
0438 status = "disabled";
0439 };
0440 };
0441 };
0442
0443 /include/ "mpc8569si-post.dtsi"
