0001 /*
0002 * MPC8568 Silicon/SoC Device Tree Source (post include)
0003 *
0004 * Copyright 2011 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 &lbc {
0036 #address-cells = <2>;
0037 #size-cells = <1>;
0038 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus";
0039 interrupts = <19 2 0 0>;
0040 sleep = <&pmc 0x08000000>;
0041 };
0042
0043 /* controller at 0x8000 */
0044 &pci0 {
0045 compatible = "fsl,mpc8540-pci";
0046 device_type = "pci";
0047 interrupts = <24 0x2 0 0>;
0048 bus-range = <0 0xff>;
0049 #interrupt-cells = <1>;
0050 #size-cells = <2>;
0051 #address-cells = <3>;
0052 sleep = <&pmc 0x80000000>;
0053 };
0054
0055 /* controller at 0xa000 */
0056 &pci1 {
0057 compatible = "fsl,mpc8548-pcie";
0058 device_type = "pci";
0059 #size-cells = <2>;
0060 #address-cells = <3>;
0061 bus-range = <0 255>;
0062 clock-frequency = <33333333>;
0063 interrupts = <26 2 0 0>;
0064 sleep = <&pmc 0x20000000>;
0065
0066 pcie@0 {
0067 reg = <0 0 0 0 0>;
0068 #interrupt-cells = <1>;
0069 #size-cells = <2>;
0070 #address-cells = <3>;
0071 device_type = "pci";
0072 interrupts = <26 2 0 0>;
0073 interrupt-map-mask = <0xf800 0 0 7>;
0074 interrupt-map = <
0075 /* IDSEL 0x0 */
0076 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
0077 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
0078 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
0079 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
0080 >;
0081 };
0082 };
0083
0084 &rio {
0085 compatible = "fsl,srio";
0086 interrupts = <48 2 0 0>;
0087 #address-cells = <2>;
0088 #size-cells = <2>;
0089 fsl,srio-rmu-handle = <&rmu>;
0090 sleep = <&pmc 0x00080000>;
0091 ranges;
0092
0093 port1 {
0094 #address-cells = <2>;
0095 #size-cells = <2>;
0096 cell-index = <1>;
0097 };
0098 };
0099
0100 &soc {
0101 #address-cells = <1>;
0102 #size-cells = <1>;
0103 device_type = "soc";
0104 compatible = "fsl,mpc8568-immr", "simple-bus";
0105 bus-frequency = <0>; // Filled out by uboot.
0106
0107 ecm-law@0 {
0108 compatible = "fsl,ecm-law";
0109 reg = <0x0 0x1000>;
0110 fsl,num-laws = <10>;
0111 };
0112
0113 ecm@1000 {
0114 compatible = "fsl,mpc8568-ecm", "fsl,ecm";
0115 reg = <0x1000 0x1000>;
0116 interrupts = <17 2 0 0>;
0117 };
0118
0119 memory-controller@2000 {
0120 compatible = "fsl,mpc8568-memory-controller";
0121 reg = <0x2000 0x1000>;
0122 interrupts = <18 2 0 0>;
0123 };
0124
0125 i2c-sleep-nexus {
0126 #address-cells = <1>;
0127 #size-cells = <1>;
0128 compatible = "simple-bus";
0129 sleep = <&pmc 0x00000004>;
0130 ranges;
0131
0132 /include/ "pq3-i2c-0.dtsi"
0133 /include/ "pq3-i2c-1.dtsi"
0134
0135 };
0136
0137 duart-sleep-nexus {
0138 #address-cells = <1>;
0139 #size-cells = <1>;
0140 compatible = "simple-bus";
0141 sleep = <&pmc 0x00000002>;
0142 ranges;
0143
0144 /include/ "pq3-duart-0.dtsi"
0145
0146 };
0147
0148 L2: l2-cache-controller@20000 {
0149 compatible = "fsl,mpc8568-l2-cache-controller";
0150 reg = <0x20000 0x1000>;
0151 cache-line-size = <32>; // 32 bytes
0152 cache-size = <0x80000>; // L2, 512K
0153 interrupts = <16 2 0 0>;
0154 };
0155
0156 /include/ "pq3-dma-0.dtsi"
0157 dma@21300 {
0158 sleep = <&pmc 0x00000400>;
0159 };
0160
0161 /include/ "pq3-etsec1-0.dtsi"
0162 ethernet@24000 {
0163 sleep = <&pmc 0x00000080>;
0164 };
0165
0166 /include/ "pq3-etsec1-1.dtsi"
0167 ethernet@25000 {
0168 sleep = <&pmc 0x00000040>;
0169 };
0170
0171 par_io@e0100 {
0172 reg = <0xe0100 0x100>;
0173 device_type = "par_io";
0174 };
0175
0176 /include/ "pq3-sec2.1-0.dtsi"
0177 crypto@30000 {
0178 sleep = <&pmc 0x01000000>;
0179 };
0180
0181 /include/ "pq3-mpic.dtsi"
0182 /include/ "pq3-rmu-0.dtsi"
0183 rmu@d3000 {
0184 sleep = <&pmc 0x00040000>;
0185 };
0186
0187 global-utilities@e0000 {
0188 #address-cells = <1>;
0189 #size-cells = <1>;
0190 compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
0191 reg = <0xe0000 0x1000>;
0192 ranges = <0 0xe0000 0x1000>;
0193 fsl,has-rstcr;
0194
0195 pmc: power@70 {
0196 compatible = "fsl,mpc8568-pmc",
0197 "fsl,mpc8548-pmc";
0198 reg = <0x70 0x20>;
0199 };
0200 };
0201 };
0202
0203 &qe {
0204 #address-cells = <1>;
0205 #size-cells = <1>;
0206 device_type = "qe";
0207 compatible = "fsl,qe";
0208 sleep = <&pmc 0x00000800>;
0209 brg-frequency = <0>;
0210 bus-frequency = <396000000>;
0211 fsl,qe-num-riscs = <2>;
0212 fsl,qe-num-snums = <28>;
0213
0214 qeic: interrupt-controller@80 {
0215 interrupt-controller;
0216 compatible = "fsl,qe-ic";
0217 #address-cells = <0>;
0218 #interrupt-cells = <1>;
0219 reg = <0x80 0x80>;
0220 interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
0221 interrupt-parent = <&mpic>;
0222 };
0223
0224 spi@4c0 {
0225 #address-cells = <1>;
0226 #size-cells = <0>;
0227 compatible = "fsl,spi";
0228 reg = <0x4c0 0x40>;
0229 cell-index = <0>;
0230 interrupts = <2>;
0231 interrupt-parent = <&qeic>;
0232 };
0233
0234 spi@500 {
0235 #address-cells = <1>;
0236 #size-cells = <0>;
0237 cell-index = <1>;
0238 compatible = "fsl,spi";
0239 reg = <0x500 0x40>;
0240 interrupts = <1>;
0241 interrupt-parent = <&qeic>;
0242 };
0243
0244 ucc@2000 {
0245 cell-index = <1>;
0246 reg = <0x2000 0x200>;
0247 interrupts = <32>;
0248 interrupt-parent = <&qeic>;
0249 };
0250
0251 ucc@3000 {
0252 cell-index = <2>;
0253 reg = <0x3000 0x200>;
0254 interrupts = <33>;
0255 interrupt-parent = <&qeic>;
0256 };
0257
0258 muram@10000 {
0259 #address-cells = <1>;
0260 #size-cells = <1>;
0261 compatible = "fsl,qe-muram", "fsl,cpm-muram";
0262 ranges = <0x0 0x10000 0x10000>;
0263
0264 data-only@0 {
0265 compatible = "fsl,qe-muram-data",
0266 "fsl,cpm-muram-data";
0267 reg = <0x0 0x10000>;
0268 };
0269 };
0270 };
