0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8568E MDS Device Tree Source
0004 *
0005 * Copyright 2007, 2008 Freescale Semiconductor Inc.
0006 */
0007
0008 /include/ "mpc8568si-pre.dtsi"
0009
0010 / {
0011 model = "MPC8568EMDS";
0012 compatible = "MPC8568EMDS", "MPC85xxMDS";
0013
0014 aliases {
0015 pci0 = &pci0;
0016 pci1 = &pci1;
0017 rapidio0 = &rio;
0018 };
0019
0020 memory {
0021 device_type = "memory";
0022 reg = <0x0 0x0 0x0 0x0>;
0023 };
0024
0025 lbc: localbus@e0005000 {
0026 reg = <0x0 0xe0005000 0x0 0x1000>;
0027 ranges = <0x0 0x0 0xfe000000 0x02000000
0028 0x1 0x0 0xf8000000 0x00008000
0029 0x2 0x0 0xf0000000 0x04000000
0030 0x4 0x0 0xf8008000 0x00008000
0031 0x5 0x0 0xf8010000 0x00008000>;
0032
0033 nor@0,0 {
0034 #address-cells = <1>;
0035 #size-cells = <1>;
0036 compatible = "cfi-flash";
0037 reg = <0x0 0x0 0x02000000>;
0038 bank-width = <2>;
0039 device-width = <2>;
0040 };
0041
0042 bcsr@1,0 {
0043 #address-cells = <1>;
0044 #size-cells = <1>;
0045 compatible = "fsl,mpc8568mds-bcsr";
0046 reg = <1 0 0x8000>;
0047 ranges = <0 1 0 0x8000>;
0048
0049 bcsr5: gpio-controller@11 {
0050 #gpio-cells = <2>;
0051 compatible = "fsl,mpc8568mds-bcsr-gpio";
0052 reg = <0x5 0x1>;
0053 gpio-controller;
0054 };
0055 };
0056
0057 pib@4,0 {
0058 compatible = "fsl,mpc8568mds-pib";
0059 reg = <4 0 0x8000>;
0060 };
0061
0062 pib@5,0 {
0063 compatible = "fsl,mpc8568mds-pib";
0064 reg = <5 0 0x8000>;
0065 };
0066 };
0067
0068 soc: soc8568@e0000000 {
0069 ranges = <0x0 0x0 0xe0000000 0x100000>;
0070
0071 i2c-sleep-nexus {
0072 i2c@3000 {
0073 rtc@68 {
0074 compatible = "dallas,ds1374";
0075 reg = <0x68>;
0076 interrupts = <3 1 0 0>;
0077 };
0078 };
0079 };
0080
0081 enet0: ethernet@24000 {
0082 tbi-handle = <&tbi0>;
0083 phy-handle = <&phy2>;
0084 };
0085
0086 mdio@24520 {
0087 phy0: ethernet-phy@7 {
0088 interrupts = <1 1 0 0>;
0089 reg = <0x7>;
0090 };
0091 phy1: ethernet-phy@1 {
0092 interrupts = <2 1 0 0>;
0093 reg = <0x1>;
0094 };
0095 phy2: ethernet-phy@2 {
0096 interrupts = <1 1 0 0>;
0097 reg = <0x2>;
0098 };
0099 phy3: ethernet-phy@3 {
0100 interrupts = <2 1 0 0>;
0101 reg = <0x3>;
0102 };
0103 tbi0: tbi-phy@11 {
0104 reg = <0x11>;
0105 device_type = "tbi-phy";
0106 };
0107 };
0108
0109 enet1: ethernet@25000 {
0110 tbi-handle = <&tbi1>;
0111 phy-handle = <&phy3>;
0112 sleep = <&pmc 0x00000040>;
0113 };
0114
0115 mdio@25520 {
0116 tbi1: tbi-phy@11 {
0117 reg = <0x11>;
0118 device_type = "tbi-phy";
0119 };
0120 };
0121
0122 par_io@e0100 {
0123 num-ports = <7>;
0124
0125 pio1: ucc_pin@1 {
0126 pio-map = <
0127 /* port pin dir open_drain assignment has_irq */
0128 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
0129 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
0130 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
0131 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
0132 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
0133 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
0134 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
0135 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
0136 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
0137 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
0138 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
0139 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
0140 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
0141 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
0142 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
0143 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
0144 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
0145 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
0146 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
0147 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
0148 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
0149 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
0150 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
0151 };
0152
0153 pio2: ucc_pin@2 {
0154 pio-map = <
0155 /* port pin dir open_drain assignment has_irq */
0156 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
0157 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
0158 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
0159 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
0160 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
0161 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
0162 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
0163 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
0164 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
0165 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
0166 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
0167 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
0168 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
0169 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
0170 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
0171 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
0172 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
0173 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
0174 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
0175 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
0176 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
0177 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
0178 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
0179 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
0180 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
0181 };
0182 };
0183 };
0184
0185 qe: qe@e0080000 {
0186 ranges = <0x0 0x0 0xe0080000 0x40000>;
0187 reg = <0x0 0xe0080000 0x0 0x480>;
0188
0189 spi@4c0 {
0190 mode = "cpu";
0191 };
0192
0193 spi@500 {
0194 mode = "cpu";
0195 };
0196
0197 enet2: ucc@2000 {
0198 device_type = "network";
0199 compatible = "ucc_geth";
0200 local-mac-address = [ 00 00 00 00 00 00 ];
0201 rx-clock-name = "none";
0202 tx-clock-name = "clk16";
0203 pio-handle = <&pio1>;
0204 phy-handle = <&phy0>;
0205 phy-connection-type = "rgmii-id";
0206 };
0207
0208 enet3: ucc@3000 {
0209 device_type = "network";
0210 compatible = "ucc_geth";
0211 local-mac-address = [ 00 00 00 00 00 00 ];
0212 rx-clock-name = "none";
0213 tx-clock-name = "clk16";
0214 pio-handle = <&pio2>;
0215 phy-handle = <&phy1>;
0216 phy-connection-type = "rgmii-id";
0217 };
0218
0219 mdio@2120 {
0220 #address-cells = <1>;
0221 #size-cells = <0>;
0222 reg = <0x2120 0x18>;
0223 compatible = "fsl,ucc-mdio";
0224
0225 /* These are the same PHYs as on
0226 * gianfar's MDIO bus */
0227 qe_phy0: ethernet-phy@7 {
0228 interrupt-parent = <&mpic>;
0229 interrupts = <1 1 0 0>;
0230 reg = <0x7>;
0231 };
0232 qe_phy1: ethernet-phy@1 {
0233 interrupt-parent = <&mpic>;
0234 interrupts = <2 1 0 0>;
0235 reg = <0x1>;
0236 };
0237 qe_phy2: ethernet-phy@2 {
0238 interrupt-parent = <&mpic>;
0239 interrupts = <1 1 0 0>;
0240 reg = <0x2>;
0241 };
0242 qe_phy3: ethernet-phy@3 {
0243 interrupt-parent = <&mpic>;
0244 interrupts = <2 1 0 0>;
0245 reg = <0x3>;
0246 };
0247 };
0248 };
0249
0250 pci0: pci@e0008000 {
0251 reg = <0x0 0xe0008000 0x0 0x1000>;
0252 ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
0253 0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
0254 clock-frequency = <66666666>;
0255 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0256 interrupt-map = <
0257 /* IDSEL 0x12 AD18 */
0258 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
0259 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
0260 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
0261 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
0262
0263 /* IDSEL 0x13 AD19 */
0264 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
0265 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
0266 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
0267 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
0268 };
0269
0270 /* PCI Express */
0271 pci1: pcie@e000a000 {
0272 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
0273 0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
0274 reg = <0x0 0xe000a000 0x0 0x1000>;
0275 pcie@0 {
0276 ranges = <0x2000000 0x0 0xa0000000
0277 0x2000000 0x0 0xa0000000
0278 0x0 0x10000000
0279
0280 0x1000000 0x0 0x0
0281 0x1000000 0x0 0x0
0282 0x0 0x800000>;
0283 };
0284 };
0285
0286 rio: rapidio@e00c00000 {
0287 reg = <0x0 0xe00c0000 0x0 0x20000>;
0288 port1 {
0289 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
0290 };
0291 };
0292
0293 leds {
0294 compatible = "gpio-leds";
0295
0296 green {
0297 gpios = <&bcsr5 1 0>;
0298 };
0299
0300 amber {
0301 gpios = <&bcsr5 2 0>;
0302 };
0303
0304 red {
0305 gpios = <&bcsr5 3 0>;
0306 };
0307 };
0308 };
0309
0310 /include/ "mpc8568si-post.dtsi"
