0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8555 CDS Device Tree Source
0004 *
0005 * Copyright 2006, 2008 Freescale Semiconductor Inc.
0006 */
0007
0008 /dts-v1/;
0009
0010 /include/ "e500v2_power_isa.dtsi"
0011
0012 / {
0013 model = "MPC8555CDS";
0014 compatible = "MPC8555CDS", "MPC85xxCDS";
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017
0018 aliases {
0019 ethernet0 = &enet0;
0020 ethernet1 = &enet1;
0021 serial0 = &serial0;
0022 serial1 = &serial1;
0023 pci0 = &pci0;
0024 pci1 = &pci1;
0025 };
0026
0027 cpus {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030
0031 PowerPC,8555@0 {
0032 device_type = "cpu";
0033 reg = <0x0>;
0034 d-cache-line-size = <32>; // 32 bytes
0035 i-cache-line-size = <32>; // 32 bytes
0036 d-cache-size = <0x8000>; // L1, 32K
0037 i-cache-size = <0x8000>; // L1, 32K
0038 timebase-frequency = <0>; // 33 MHz, from uboot
0039 bus-frequency = <0>; // 166 MHz
0040 clock-frequency = <0>; // 825 MHz, from uboot
0041 next-level-cache = <&L2>;
0042 };
0043 };
0044
0045 memory {
0046 device_type = "memory";
0047 reg = <0x0 0x8000000>; // 128M at 0x0
0048 };
0049
0050 soc8555@e0000000 {
0051 #address-cells = <1>;
0052 #size-cells = <1>;
0053 device_type = "soc";
0054 compatible = "simple-bus";
0055 ranges = <0x0 0xe0000000 0x100000>;
0056 bus-frequency = <0>;
0057
0058 ecm-law@0 {
0059 compatible = "fsl,ecm-law";
0060 reg = <0x0 0x1000>;
0061 fsl,num-laws = <8>;
0062 };
0063
0064 ecm@1000 {
0065 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
0066 reg = <0x1000 0x1000>;
0067 interrupts = <17 2>;
0068 interrupt-parent = <&mpic>;
0069 };
0070
0071 memory-controller@2000 {
0072 compatible = "fsl,mpc8555-memory-controller";
0073 reg = <0x2000 0x1000>;
0074 interrupt-parent = <&mpic>;
0075 interrupts = <18 2>;
0076 };
0077
0078 L2: l2-cache-controller@20000 {
0079 compatible = "fsl,mpc8555-l2-cache-controller";
0080 reg = <0x20000 0x1000>;
0081 cache-line-size = <32>; // 32 bytes
0082 cache-size = <0x40000>; // L2, 256K
0083 interrupt-parent = <&mpic>;
0084 interrupts = <16 2>;
0085 };
0086
0087 i2c@3000 {
0088 #address-cells = <1>;
0089 #size-cells = <0>;
0090 cell-index = <0>;
0091 compatible = "fsl-i2c";
0092 reg = <0x3000 0x100>;
0093 interrupts = <43 2>;
0094 interrupt-parent = <&mpic>;
0095 dfsrr;
0096 };
0097
0098 dma@21300 {
0099 #address-cells = <1>;
0100 #size-cells = <1>;
0101 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
0102 reg = <0x21300 0x4>;
0103 ranges = <0x0 0x21100 0x200>;
0104 cell-index = <0>;
0105 dma-channel@0 {
0106 compatible = "fsl,mpc8555-dma-channel",
0107 "fsl,eloplus-dma-channel";
0108 reg = <0x0 0x80>;
0109 cell-index = <0>;
0110 interrupt-parent = <&mpic>;
0111 interrupts = <20 2>;
0112 };
0113 dma-channel@80 {
0114 compatible = "fsl,mpc8555-dma-channel",
0115 "fsl,eloplus-dma-channel";
0116 reg = <0x80 0x80>;
0117 cell-index = <1>;
0118 interrupt-parent = <&mpic>;
0119 interrupts = <21 2>;
0120 };
0121 dma-channel@100 {
0122 compatible = "fsl,mpc8555-dma-channel",
0123 "fsl,eloplus-dma-channel";
0124 reg = <0x100 0x80>;
0125 cell-index = <2>;
0126 interrupt-parent = <&mpic>;
0127 interrupts = <22 2>;
0128 };
0129 dma-channel@180 {
0130 compatible = "fsl,mpc8555-dma-channel",
0131 "fsl,eloplus-dma-channel";
0132 reg = <0x180 0x80>;
0133 cell-index = <3>;
0134 interrupt-parent = <&mpic>;
0135 interrupts = <23 2>;
0136 };
0137 };
0138
0139 enet0: ethernet@24000 {
0140 #address-cells = <1>;
0141 #size-cells = <1>;
0142 cell-index = <0>;
0143 device_type = "network";
0144 model = "TSEC";
0145 compatible = "gianfar";
0146 reg = <0x24000 0x1000>;
0147 ranges = <0x0 0x24000 0x1000>;
0148 local-mac-address = [ 00 00 00 00 00 00 ];
0149 interrupts = <29 2 30 2 34 2>;
0150 interrupt-parent = <&mpic>;
0151 tbi-handle = <&tbi0>;
0152 phy-handle = <&phy0>;
0153
0154 mdio@520 {
0155 #address-cells = <1>;
0156 #size-cells = <0>;
0157 compatible = "fsl,gianfar-mdio";
0158 reg = <0x520 0x20>;
0159
0160 phy0: ethernet-phy@0 {
0161 interrupt-parent = <&mpic>;
0162 interrupts = <5 1>;
0163 reg = <0x0>;
0164 };
0165 phy1: ethernet-phy@1 {
0166 interrupt-parent = <&mpic>;
0167 interrupts = <5 1>;
0168 reg = <0x1>;
0169 };
0170 tbi0: tbi-phy@11 {
0171 reg = <0x11>;
0172 device_type = "tbi-phy";
0173 };
0174 };
0175 };
0176
0177 enet1: ethernet@25000 {
0178 #address-cells = <1>;
0179 #size-cells = <1>;
0180 cell-index = <1>;
0181 device_type = "network";
0182 model = "TSEC";
0183 compatible = "gianfar";
0184 reg = <0x25000 0x1000>;
0185 ranges = <0x0 0x25000 0x1000>;
0186 local-mac-address = [ 00 00 00 00 00 00 ];
0187 interrupts = <35 2 36 2 40 2>;
0188 interrupt-parent = <&mpic>;
0189 tbi-handle = <&tbi1>;
0190 phy-handle = <&phy1>;
0191
0192 mdio@520 {
0193 #address-cells = <1>;
0194 #size-cells = <0>;
0195 compatible = "fsl,gianfar-tbi";
0196 reg = <0x520 0x20>;
0197
0198 tbi1: tbi-phy@11 {
0199 reg = <0x11>;
0200 device_type = "tbi-phy";
0201 };
0202 };
0203 };
0204
0205 serial0: serial@4500 {
0206 cell-index = <0>;
0207 device_type = "serial";
0208 compatible = "fsl,ns16550", "ns16550";
0209 reg = <0x4500 0x100>; // reg base, size
0210 clock-frequency = <0>; // should we fill in in uboot?
0211 interrupts = <42 2>;
0212 interrupt-parent = <&mpic>;
0213 };
0214
0215 serial1: serial@4600 {
0216 cell-index = <1>;
0217 device_type = "serial";
0218 compatible = "fsl,ns16550", "ns16550";
0219 reg = <0x4600 0x100>; // reg base, size
0220 clock-frequency = <0>; // should we fill in in uboot?
0221 interrupts = <42 2>;
0222 interrupt-parent = <&mpic>;
0223 };
0224
0225 crypto@30000 {
0226 compatible = "fsl,sec2.0";
0227 reg = <0x30000 0x10000>;
0228 interrupts = <45 2>;
0229 interrupt-parent = <&mpic>;
0230 fsl,num-channels = <4>;
0231 fsl,channel-fifo-len = <24>;
0232 fsl,exec-units-mask = <0x7e>;
0233 fsl,descriptor-types-mask = <0x01010ebf>;
0234 };
0235
0236 mpic: pic@40000 {
0237 interrupt-controller;
0238 #address-cells = <0>;
0239 #interrupt-cells = <2>;
0240 reg = <0x40000 0x40000>;
0241 compatible = "chrp,open-pic";
0242 device_type = "open-pic";
0243 };
0244
0245 cpm@919c0 {
0246 #address-cells = <1>;
0247 #size-cells = <1>;
0248 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
0249 reg = <0x919c0 0x30>;
0250 ranges;
0251
0252 muram@80000 {
0253 #address-cells = <1>;
0254 #size-cells = <1>;
0255 ranges = <0x0 0x80000 0x10000>;
0256
0257 data@0 {
0258 compatible = "fsl,cpm-muram-data";
0259 reg = <0x0 0x2000 0x9000 0x1000>;
0260 };
0261 };
0262
0263 brg@919f0 {
0264 compatible = "fsl,mpc8555-brg",
0265 "fsl,cpm2-brg",
0266 "fsl,cpm-brg";
0267 reg = <0x919f0 0x10 0x915f0 0x10>;
0268 };
0269
0270 cpmpic: pic@90c00 {
0271 interrupt-controller;
0272 #address-cells = <0>;
0273 #interrupt-cells = <2>;
0274 interrupts = <46 2>;
0275 interrupt-parent = <&mpic>;
0276 reg = <0x90c00 0x80>;
0277 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
0278 };
0279 };
0280 };
0281
0282 pci0: pci@e0008000 {
0283 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
0284 interrupt-map = <
0285
0286 /* IDSEL 0x10 */
0287 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
0288 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
0289 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
0290 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
0291
0292 /* IDSEL 0x11 */
0293 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
0294 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
0295 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
0296 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
0297
0298 /* IDSEL 0x12 (Slot 1) */
0299 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
0300 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
0301 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
0302 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
0303
0304 /* IDSEL 0x13 (Slot 2) */
0305 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
0306 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
0307 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
0308 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
0309
0310 /* IDSEL 0x14 (Slot 3) */
0311 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
0312 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
0313 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
0314 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
0315
0316 /* IDSEL 0x15 (Slot 4) */
0317 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
0318 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
0319 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
0320 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
0321
0322 /* Bus 1 (Tundra Bridge) */
0323 /* IDSEL 0x12 (ISA bridge) */
0324 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
0325 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
0326 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
0327 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
0328 interrupt-parent = <&mpic>;
0329 interrupts = <24 2>;
0330 bus-range = <0 0>;
0331 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0332 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
0333 clock-frequency = <66666666>;
0334 #interrupt-cells = <1>;
0335 #size-cells = <2>;
0336 #address-cells = <3>;
0337 reg = <0xe0008000 0x1000>;
0338 compatible = "fsl,mpc8540-pci";
0339 device_type = "pci";
0340
0341 i8259@19000 {
0342 interrupt-controller;
0343 device_type = "interrupt-controller";
0344 reg = <0x19000 0x0 0x0 0x0 0x1>;
0345 #address-cells = <0>;
0346 #interrupt-cells = <2>;
0347 compatible = "chrp,iic";
0348 interrupts = <1>;
0349 interrupt-parent = <&pci0>;
0350 };
0351 };
0352
0353 pci1: pci@e0009000 {
0354 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0355 interrupt-map = <
0356
0357 /* IDSEL 0x15 */
0358 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
0359 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
0360 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
0361 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
0362 interrupt-parent = <&mpic>;
0363 interrupts = <25 2>;
0364 bus-range = <0 0>;
0365 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0366 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
0367 clock-frequency = <66666666>;
0368 #interrupt-cells = <1>;
0369 #size-cells = <2>;
0370 #address-cells = <3>;
0371 reg = <0xe0009000 0x1000>;
0372 compatible = "fsl,mpc8540-pci";
0373 device_type = "pci";
0374 };
0375 };
