0001 /*
0002 * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
0003 *
0004 * Copyright 2012 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 &board_lbc {
0036 nor@0,0 {
0037 #address-cells = <1>;
0038 #size-cells = <1>;
0039 compatible = "cfi-flash";
0040 reg = <0x0 0x0 0x01000000>;
0041 bank-width = <2>;
0042 device-width = <2>;
0043
0044 partition@0 {
0045 reg = <0x0 0x0b00000>;
0046 label = "ramdisk-nor";
0047 };
0048
0049 partition@300000 {
0050 reg = <0x0b00000 0x0400000>;
0051 label = "kernel-nor";
0052 };
0053
0054 partition@700000 {
0055 reg = <0x0f00000 0x060000>;
0056 label = "dtb-nor";
0057 };
0058
0059 partition@760000 {
0060 reg = <0x0f60000 0x020000>;
0061 label = "env-nor";
0062 read-only;
0063 };
0064
0065 partition@780000 {
0066 reg = <0x0f80000 0x080000>;
0067 label = "u-boot-nor";
0068 read-only;
0069 };
0070 };
0071
0072 board-control@1,0 {
0073 compatible = "fsl,mpc8548cds-fpga";
0074 reg = <0x1 0x0 0x1000>;
0075 };
0076 };
0077
0078 &board_soc {
0079 i2c@3000 {
0080 eeprom@50 {
0081 compatible = "atmel,24c64";
0082 reg = <0x50>;
0083 };
0084
0085 eeprom@56 {
0086 compatible = "atmel,24c64";
0087 reg = <0x56>;
0088 };
0089
0090 eeprom@57 {
0091 compatible = "atmel,24c64";
0092 reg = <0x57>;
0093 };
0094 };
0095
0096 i2c@3100 {
0097 eeprom@50 {
0098 compatible = "atmel,24c64";
0099 reg = <0x50>;
0100 };
0101 };
0102
0103 enet0: ethernet@24000 {
0104 tbi-handle = <&tbi0>;
0105 phy-handle = <&phy0>;
0106 };
0107
0108 mdio@24520 {
0109 phy0: ethernet-phy@0 {
0110 interrupts = <5 1 0 0>;
0111 reg = <0x0>;
0112 };
0113 phy1: ethernet-phy@1 {
0114 interrupts = <5 1 0 0>;
0115 reg = <0x1>;
0116 };
0117 phy2: ethernet-phy@2 {
0118 interrupts = <5 1 0 0>;
0119 reg = <0x2>;
0120 };
0121 phy3: ethernet-phy@3 {
0122 interrupts = <5 1 0 0>;
0123 reg = <0x3>;
0124 };
0125 tbi0: tbi-phy@11 {
0126 reg = <0x11>;
0127 device_type = "tbi-phy";
0128 };
0129 };
0130
0131 enet1: ethernet@25000 {
0132 tbi-handle = <&tbi1>;
0133 phy-handle = <&phy1>;
0134 };
0135
0136 mdio@25520 {
0137 tbi1: tbi-phy@11 {
0138 reg = <0x11>;
0139 device_type = "tbi-phy";
0140 };
0141 };
0142
0143 enet2: ethernet@26000 {
0144 tbi-handle = <&tbi2>;
0145 phy-handle = <&phy2>;
0146 };
0147
0148 mdio@26520 {
0149 tbi2: tbi-phy@11 {
0150 reg = <0x11>;
0151 device_type = "tbi-phy";
0152 };
0153 };
0154
0155 enet3: ethernet@27000 {
0156 tbi-handle = <&tbi3>;
0157 phy-handle = <&phy3>;
0158 };
0159
0160 mdio@27520 {
0161 tbi3: tbi-phy@11 {
0162 reg = <0x11>;
0163 device_type = "tbi-phy";
0164 };
0165 };
0166 };
0167
0168 &board_pci0 {
0169 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0170 interrupt-map = <
0171 /* IDSEL 0x4 (PCIX Slot 2) */
0172 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0173 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0174 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0175 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
0176
0177 /* IDSEL 0x5 (PCIX Slot 3) */
0178 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
0179 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
0180 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
0181 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
0182
0183 /* IDSEL 0x6 (PCIX Slot 4) */
0184 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
0185 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
0186 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
0187 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
0188
0189 /* IDSEL 0x8 (PCIX Slot 5) */
0190 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0191 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0192 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0193 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
0194
0195 /* IDSEL 0xC (Tsi310 bridge) */
0196 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0197 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0198 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0199 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
0200
0201 /* IDSEL 0x14 (Slot 2) */
0202 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0203 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0204 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0205 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
0206
0207 /* IDSEL 0x15 (Slot 3) */
0208 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
0209 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
0210 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
0211 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
0212
0213 /* IDSEL 0x16 (Slot 4) */
0214 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
0215 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
0216 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
0217 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
0218
0219 /* IDSEL 0x18 (Slot 5) */
0220 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0221 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0222 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0223 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
0224
0225 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
0226 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0227 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0228 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0229 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
0230
0231 pci_bridge@1c {
0232 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0233 interrupt-map = <
0234
0235 /* IDSEL 0x00 (PrPMC Site) */
0236 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0237 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0238 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0239 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
0240
0241 /* IDSEL 0x04 (VIA chip) */
0242 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0243 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0244 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0245 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
0246
0247 /* IDSEL 0x05 (8139) */
0248 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
0249
0250 /* IDSEL 0x06 (Slot 6) */
0251 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
0252 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
0253 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
0254 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
0255
0256 /* IDESL 0x07 (Slot 7) */
0257 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
0258 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
0259 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
0260 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
0261
0262 reg = <0xe000 0x0 0x0 0x0 0x0>;
0263 #interrupt-cells = <1>;
0264 #size-cells = <2>;
0265 #address-cells = <3>;
0266 ranges = <0x2000000 0x0 0x80000000
0267 0x2000000 0x0 0x80000000
0268 0x0 0x20000000
0269 0x1000000 0x0 0x0
0270 0x1000000 0x0 0x0
0271 0x0 0x80000>;
0272 clock-frequency = <33333333>;
0273
0274 isa@4 {
0275 device_type = "isa";
0276 #interrupt-cells = <2>;
0277 #size-cells = <1>;
0278 #address-cells = <2>;
0279 reg = <0x2000 0x0 0x0 0x0 0x0>;
0280 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
0281 interrupt-parent = <&i8259>;
0282
0283 i8259: interrupt-controller@20 {
0284 interrupt-controller;
0285 device_type = "interrupt-controller";
0286 reg = <0x1 0x20 0x2
0287 0x1 0xa0 0x2
0288 0x1 0x4d0 0x2>;
0289 #address-cells = <0>;
0290 #interrupt-cells = <2>;
0291 compatible = "chrp,iic";
0292 interrupts = <0 1 0 0>;
0293 interrupt-parent = <&mpic>;
0294 };
0295
0296 rtc@70 {
0297 compatible = "pnpPNP,b00";
0298 reg = <0x1 0x70 0x2>;
0299 };
0300 };
0301 };
0302 };
